Abstract:
A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.
Abstract:
A digital system has a substrate having a top surface on which a waveguide is formed on the top surface of the substrate. The waveguide is formed by a conformal base layer formed on the top surface of the substrate, two spaced apart sidewalls, and a top conformal layer connected to the base layer to form a longitudinal core region. The waveguide may be a metallic or otherwise conductive waveguide, a dielectric waveguide, a micro-coax, etc.
Abstract:
A dielectric waveguide (DWG) has a longitudinal core member with a first dielectric constant value surrounded by a cladding with a cladding dielectric constant value that is lower than the first dielectric constant value. A first port of a signal divider is connected to receive a signal from the DWG. A second port and a third port are each configured to output a portion of the signal received on the first port, wherein the first and second port are approximately in line and the third port is at an angle to a line formed by the first port and the second port. The first port and second port have a core member with the first dielectric constant value, and the third port has a core member with a second dielectric constant value that is higher than the first dielectric constant value.
Abstract:
Described examples include methods of fabricating conductive and resistive structures by direct-write variable impedance patterning using nanoparticle-based metallization layers or chemical reaction-based deposition. In some examples, a low conductivity nanoparticle material is deposited over a surface. The nanoparticle material is selectively illuminated at different applied energy levels via illumination source power adjustments and/or scan rate adjustments for selective patterned sintering to create conductive circuit structures as well as resistive circuit structures including gradient resistive circuit structures having an electrical resistivity profile that varies along the structure length. Further examples include methods in which a non-conductive reactant layer is deposited or patterned, and a second solution is deposited in varying amounts using an additive deposition for reaction with the reactant layer to form controllably conductive structures.
Abstract:
A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the multilayer substrate. A set of densely spaced vias form two sidewalls of the horn antenna by coupling adjacent edges of the top plate and the bottom plate. The horn antenna has a narrow input end and a wider flare end. A microstrip line is coupled to the top plate and a ground plane element is coupled to the bottom plate at the input end of the horn antenna.
Abstract:
A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.
Abstract:
A dielectric waveguide interconnect system has a dielectric waveguide (DWG) a core surrounded by a cladding along the length of the DWG. One or more periodic structures are embedded along the length of the DWG such that the core of the DWG is integral to each of the one or more periodic structures.
Abstract:
A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant.
Abstract:
A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the multilayer substrate. A set of densely spaced vias form two sidewalls of the horn antenna by coupling adjacent edges of the top plate and the bottom plate. The horn antenna has a narrow input end and a wider flare end. A microstrip line is coupled to the top plate and a ground plane element is coupled to the bottom plate at the input end of the horn antenna.
Abstract:
A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.