公开(公告)号：US20220036931A1

公开(公告)日：2022-02-03

申请号：US17081380

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L27/11597 ,  H01L27/105 ,  H01L21/822 ,  H01L21/8239

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US20220020770A1

公开(公告)日：2022-01-20

申请号：US17018114

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  G11C5/06

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US20210375919A1

公开(公告)日：2021-12-02

申请号：US17122228

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/522

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

公开(公告)号：US11133306B2

公开(公告)日：2021-09-28

申请号：US16547292

申请日：2019-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Tsung-Chieh Hsiao

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/161

Abstract: A semiconductor device includes device areas where a Fin FET is disposed and a non-device area disposed between the device areas, which includes a dummy structure. The Fin FET includes a fin structure having a well region including a first semiconductor layer, a stressor region including a second semiconductor layer and a channel region including a third semiconductor layer; an isolation region in which the well region is embedded, and from which at least an upper port of the channel region is exposed; a gate structure disposed over a part of the fin structure. The dummy structure in the non-device area includes a first dummy layer formed over the first semiconductor layer and made of a different material from the stressor region, and a second dummy layer formed over the first dummy layer and made of a different material from the channel region.

公开(公告)号：US20200303522A1

公开(公告)日：2020-09-24

申请号：US16895417

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12

Abstract: A method includes forming a first fin and a second fin protruding from a semiconductor substrate and defined by a fin height, forming a spacer layer over the first fin and the second fin, etching the spacer layer to form inner spacers and outer spacers along opposite sidewalls of each of the first fin and the second fin, where the inner spacers are formed between the first fin and the second fin and where etching the spacer layer results in the inner spacers to extend above the outer spacers, forming a source/drain (S/D) recess in each of the first fin and the second fin, and forming an epitaxial semiconductor layer in the S/D recesses, where forming the epitaxial semiconductor layer forms an air gap with the inner spacers.

公开(公告)号：US10680084B2

公开(公告)日：2020-06-09

申请号：US15962500

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84

Abstract: Epitaxial structures of a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure including two fins, inner and outer fin spacers formed along both sidewalls of the fins, and isolation regions formed around the fins. The FinFET device further includes a gate structure formed over the fin structure and an epitaxial structure formed over the fin structure in a source/drain region. The epitaxial structure is formed by merging the fins with at least one epitaxial semiconductor layer and includes an air gap having a volume determined by the height and separation distance of the inner fin spacers.

公开(公告)号：US20190148528A1

公开(公告)日：2019-05-16

申请号：US15962500

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02

Abstract: Epitaxial structures of a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure including two fins, inner and outer fin spacers formed along both sidewalls of the fins, and isolation regions formed around the fins. The FinFET device further includes a gate structure formed over the fin structure and an epitaxial structure formed over the fin structure in a source/drain region. The epitaxial structure is formed by merging the fins with at least one epitaxial semiconductor layer and includes an air gap having a volume determined by the height and separation distance of the inner fin spacers.

公开(公告)号：US10103146B2

公开(公告)日：2018-10-16

申请号：US15838451

申请日：2017-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

公开(公告)号：US10062688B2

公开(公告)日：2018-08-28

申请号：US14987509

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Tsung-Yao Wen ,  Yen-Ming Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L27/0886 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a fin extending along a first direction over a substrate and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and a first insulating gate sidewall on a first lateral surface of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate structure. A portion of the source/drain region extends under the insulating gate sidewall for a substantially constant distance along the first direction.

公开(公告)号：US20180175175A1

公开(公告)日：2018-06-21

申请号：US15653720

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.