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    Method for producing SOI & non-SOI circuits on a single wafer
    111.
    发明授权
    Method for producing SOI & non-SOI circuits on a single wafer 失效
    在单个晶片上制造SOI和非SOI电路的方法

    公开(公告)号：US5956597A

    公开(公告)日：1999-09-21

    申请号：US929730

    申请日：1997-09-15

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

    CPC分类号： H01L27/0922 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203

    摘要： According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.2 region is formed for the SOI devices, the expansion of the SOI region will bring the surface of the SOI device area up to the overall surface of the wafer. A short Chemical Mechanical Polish (CMP) step may also be included to ensure uniformity of the wafer's surface.

    摘要翻译： 根据本发明的优选实施例，形成在晶片上的应力减小区允许标准体CMOS（非SOI）器件和SOI器件可靠地制造在同一晶片上。 通常存在于SOI器件区域和非SOI器件区域之间的高应力界面被转移到高应力将被降低和放松的区域。 通常，这意味着高应力界面将被制造成位于类似于浅沟槽隔离（STI）区域的晶片的区域上。 此外，通过使用本发明的另一优选实施例，可以为包括本体CMOS器件和SOI器件的晶片保持共面的晶片表面。 这通过在氧注入之前在SOI器件区域中蚀刻硅晶片来实现，使得应力界面区域之间的区域的表面低于晶片的其余部分的整个表面。 然后，当为SOI器件形成SiO 2区域时，SOI区域的扩展将使SOI器件面的表面达到晶片的整个表面。 也可以包括一个简短的化学机械抛光（CMP）步骤，以确保晶圆表面的均匀性。

    High capacitance storage node structures
    112.
    发明授权
    High capacitance storage node structures 失效
    高电容存储节点结构

    公开(公告)号：US06391426B1

    公开(公告)日：2002-05-21

    申请号：US08878136

    申请日：1997-06-19

    申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    IPC分类号： B32B100

    CPC分类号： H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085 ,  Y10S430/168 ,  Y10T428/24355 ,  Y10T428/24628

    摘要： A high capacitance storage node structure is created in a substrate by patterning a hybrid resist (12) to produce both negative tone (16) and positive tone (18) areas in the exposed region (14). After removal of the positive tone areas (18), the substrate (12) is etched using the unexposed hybrid resist (12) and negative tone area (16) as a mask. This produces a trench (22) in the substrate (12) with a centrally located, upwardly projecting protrusion (24). The capacitor (26) is then created by coating the sidewalls of the trench (22) and protrusion (24) with dielectric (28) and filling the trench with conductive material (30) such as polysilicon.

    摘要翻译： 通过在混合抗蚀剂（12）中图案化以在曝光区域（14）中产生负色调（16）和正色调（18）区域，在衬底中形成高电容存储节点结构。 在去除正色调区域（18）之后，使用未曝光的混合抗蚀剂（12）和负色调区域（16）作为掩模蚀刻衬底（12）。 这在基板（12）中产生具有中心定位的向上突出的突起（24）的沟槽（22）。 然后通过用电介质（28）涂覆沟槽（22）和突起（24）的侧壁并用诸如多晶硅的导电材料（30）填充沟槽来产生电容器（26）。

    Resist image reversal by means of spun-on-glass
    114.
    发明授权
    Resist image reversal by means of spun-on-glass 失效
    通过旋转玻璃抵抗图像反转

    公开(公告)号：US06221562B1

    公开(公告)日：2001-04-24

    申请号：US09192137

    申请日：1998-11-13

    申请人： Diane C. Boyd ,  Toshiharu Furukawa ,  Steven J. Holmes ,  William H. Ma ,  Paul A. Rabidoux ,  David V. Horak

    发明人： Diane C. Boyd ,  Toshiharu Furukawa ,  Steven J. Holmes ,  William H. Ma ,  Paul A. Rabidoux ,  David V. Horak

    IPC分类号： G03F700

    CPC分类号： H01L21/0337 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/32139

    摘要： An image reversal method of turning hybrid photoresist spaces into resist lines for sub-feature size applications. The sub-feature size space width of the high resolution hybrid photoresist is largely independent of the lithographic process and mask reticles. These sub-feature size spaces formed by the hybrid resist are then turned into sub-feature size lines using Spin-On-Glass, SOG. The SOG is first coated over the entire patterned hybrid resist to fill in the hybrid spaces and cover the photoresist. SOG is then recessed back to expose the photoresist layer. The exposed photoresist is then removed. The sub-feature size lines are then left behind as a mask to pattern the same onto the underlying films on the substrate.

    摘要翻译： 将混合光致抗蚀剂空间转换成用于子特征尺寸应用的抗蚀剂线的图像反转方法。 高分辨率混合光致抗蚀剂的子特征尺寸空间宽度在很大程度上独立于光刻工艺和掩模掩模版。 然后，使用旋转玻璃，SOG将由混合抗蚀剂形成的这些子特征尺寸空间变成子特征尺寸线。 SOG首先涂覆在整个图案化的混合抗蚀剂上以填充混合空间并覆盖光致抗蚀剂。 然后将SOG凹进来露出光致抗蚀剂层。 然后除去曝光的光致抗蚀剂。 然后将子特征尺寸线作为掩模留下以将其图案化到衬底上的下面的膜上。

    Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors
    117.
    发明申请
    Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors 有权
    通过串联电阻同时调节多个存储单元

    公开(公告)号：US20080185652A1

    公开(公告)日：2008-08-07

    申请号：US12060922

    申请日：2008-04-02

    申请人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

    发明人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

    IPC分类号： H01L23/62 ,  H01L21/8234

    CPC分类号： H01L27/0629 ,  H01L27/101 ,  H01L27/24

    摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

    摘要翻译： 公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。 该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。 具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。 在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

    Borderless wordline for DRAM cell
    119.
    发明授权
    Borderless wordline for DRAM cell 失效
    DRAM单元的无边界字线

    公开(公告)号：US06271555B1

    公开(公告)日：2001-08-07

    申请号：US09052403

    申请日：1998-03-31

    申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

    发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

    IPC分类号： H01L27108

    CPC分类号： H01L27/10873 ,  H01L27/10891 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

    摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.

    摘要翻译： 公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。 栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。 晶体管还具有具有源/漏区的单晶半导体衬底。 主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。 电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。 围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。 位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。 还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

    Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby
    120.
    发明授权
    Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby 失效
    用于存储单元中的传送装置和存储电容器之间的互连的方法以及由此形成的装置

    公开(公告)号：US06767789B1

    公开(公告)日：2004-07-27

    申请号：US09105739

    申请日：1998-06-26

    申请人： Gary B. Bronner ,  David V. Horak ,  Toshiharu Furukawa ,  Jack A Mandelman

    发明人： Gary B. Bronner ,  David V. Horak ,  Toshiharu Furukawa ,  Jack A Mandelman

    IPC分类号： H01L31119

    CPC分类号： H01L27/10867 ,  H01L23/535 ,  H01L27/10832 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The preferred embodiment of the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a “lip” at its top on the side the connection is to be made. To form the connection, dopant is diffused from the lower surface of the capacitor step and into the substrate, forming a surface strap to connect between the storage capacitor and the transfer device. This surface strap has the advantage of being self aligned with the storage capacitor and the transfer device, facilitating higher memory cell densities. The present invention can be used to form connections between storage capacitors and memory cells in a wide variety of devices.

    摘要翻译： 本发明的优选实施例提供了用于在存储单元中的存储电容器和转移装置之间连接的独特结构及其制造方法。 本发明的优选实施例形成了在其连接将要制造的一侧的顶部具有“唇形”的电容器结构。 为了形成连接，掺杂剂从电容器台阶的下表面扩散到衬底中，形成表面带以连接存储电容器和转移装置。 该表面带具有与存储电容器和转移装置自对准的优点，便于更高的存储单元密度。 本发明可用于在各种设备中形成存储电容器和存储器单元之间的连接。