公开(公告)号：US20150067310A1

公开(公告)日：2015-03-05

申请号：US14281657

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Darius D. Gaskins

IPC: G06F9/44

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract translation: 微处理器包括多个处理核心和配置寄存器，配置寄存器被配置为指示多个处理核心中的每一个是启用还是禁用。 所述多个处理核心中的每一个启用的一个处理核心被配置为在第一情况下读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于配置寄存器的读取生成相应的配置相关值 一审。 配置寄存器被更新以指示多个处理核心中先前启用的一个处理核心被禁用。 所述多个处理核心中的每一个被配置为在第二实例中读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于对配置寄存器的读取生成相应的配置相关值 第二例。

公开(公告)号：US20150067250A1

公开(公告)日：2015-03-05

申请号：US14281585

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F12/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

Abstract translation: 微处理器包括多个处理核心，由多个处理核心共享的资源以及由非结构化地址空间内的多个处理核心中的每一个可读和写的硬件信号量。 多个处理核心中的每一个被配置为写入硬件信号量以请求所有权共享资源并从硬件信号量读取以确定是否获得所有权。 多个处理核心中的每一个被配置为写入硬件信号量以放弃共享资源的所有权。

公开(公告)号：US20150058610A1

公开(公告)日：2015-02-26

申请号：US13972657

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F9/44

CPC classification number: G06F9/4403

Abstract: An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.

公开(公告)号：US20150058565A1

公开(公告)日：2015-02-26

申请号：US13972741

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F3/06 ,  G11C17/16

CPC classification number: G06F15/177 ,  G11C17/16 ,  G11C29/785

Abstract: An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.

公开(公告)号：US20150058563A1

公开(公告)日：2015-02-26

申请号：US13972358

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F3/06 ,  G11C17/16 ,  G06F12/08

CPC classification number: G06F15/177 ,  G06F12/0802 ,  G11C17/16 ,  G11C29/785

Abstract: An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

Abstract translation: 设想用于在多核微处理器中存储和解压缩配置数据的装置。 该装置包括共享熔丝阵列和多个微处理器核。 共享保险丝阵列设置在管芯上并且包括用压缩配置数据编程的多个半导体保险丝。 多个微处理器核心也设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化内部的元件 多个核心中的每一个。 多个核心中的每一个具有复位控制器，其被配置为解压缩所有压缩的配置数据，并且分发解压缩的配置数据以初始化元件。