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    Image sensor with high quantum efficiency
    112.
    发明授权
    Image sensor with high quantum efficiency 有权

    公开(公告)号：US12243898B2

    公开(公告)日：2025-03-04

    申请号：US17207378

    申请日：2021-03-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Feng-Chien Hsieh ,  Hsin-Chi Chen ,  Kuo-Cheng Lee ,  Yun-Wei Cheng

    IPC: H01L27/146

    Abstract: The present disclosure describes an image sensor device and a method for forming the same. The image sensor device can include a semiconductor layer. The semiconductor layer can include a first surface and a second surface. The image sensor device can further include an interconnect structure formed over the first surface of the semiconductor layer, first and second radiation sensing regions formed in the second surface of the semiconductor layer, a metal stack formed over the second radiation sensing region, and a passivation layer formed through the metal stack and over a top surface of the first radiation sensing region. The metal stack can be between the passivation layer and an other top surface of the second radiation sensing region.

    Through-circuit vias in interconnect structures
    113.
    发明授权
    Through-circuit vias in interconnect structures 有权

    公开(公告)号：US12243805B2

    公开(公告)日：2025-03-04

    申请号：US17815997

    申请日：2022-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Hong Lin ,  Hsin-Chun Chang ,  Ming-Hong Hsieh ,  Ming-Yih Wang ,  Yinlung Lu

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

    Semiconductor device and methods of forming the same
    114.
    发明授权
    Semiconductor device and methods of forming the same 有权

    公开(公告)号：US12243786B2

    公开(公告)日：2025-03-04

    申请号：US17744334

    申请日：2022-05-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Da-Yuan Lee ,  Chi On Chui

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.

    Silicon phosphide semiconductor device
    115.
    发明授权
    Silicon phosphide semiconductor device 有权

    公开(公告)号：US12243784B2

    公开(公告)日：2025-03-04

    申请号：US18354801

    申请日：2023-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzu-Ching Lin ,  Tuoh Bin Ng

    IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

    Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.

    Semiconductor Device and Method
    118.
    发明申请
    Semiconductor Device and Method 有权

    公开(公告)号：US20250070064A1

    公开(公告)日：2025-02-27

    申请号：US18403064

    申请日：2024-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Hsin-Feng Chen ,  Tsung-Chieh Hsiao ,  Chih Chuan Su ,  Dian-Hau Chen

    IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

    Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

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