公开(公告)号：US20030183875A1

公开(公告)日：2003-10-02

申请号：US10330025

申请日：2002-12-27

发明人： Atsuo Isobe ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Shunpei Yamazaki ,  Mai Akiba

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L21/02683 ,  H01L21/2022 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696

摘要： It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed on a substrate, and a semiconductor film is formed on the insulation film. Due to this, preferentially formed is a region in the semiconductor film to be concentratedly applied by stress during crystallization with laser light. Specifically, a stripe-formed or rectangular concavo-convex is formed on the semiconductor film. Continuous-oscillation laser light is irradiated along the striped concavo-convex or along a direction of a longer or shorter axis of rectangle.

摘要翻译： 提供一种使用能够防止在TFT沟道区域中形成晶界的激光晶体化方法的半导体器件制造系统的问题，并且进一步防止由于晶界引起的TFT迁移率的明显降低，导通电流降低或截止电流增加 。 在基板上形成绝缘膜，在绝缘膜上形成半导体膜。 由此，优选形成半导体膜中通过激光在结晶期间通过应力集中施加的区域。 具体地，在半导体膜上形成条状或矩形凹凸。 连续振荡激光沿着条纹凹凸或长轴或短轴方向照射。

公开(公告)号：US20030178680A1

公开(公告)日：2003-09-25

申请号：US10396950

申请日：2003-03-24

发明人： Brian Roberds ,  Doulgas W. Barlage

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78609 ,  H01L29/78639

摘要： The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.

公开(公告)号：US20030168700A1

公开(公告)日：2003-09-11

申请号：US10382855

申请日：2003-03-07

申请人： FUJITSU LIMITED

发明人： Takashi Mimura ,  Keiji Ikeda

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/78696 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78684 ,  H01L29/78687

摘要： The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed on the semiconductor layer on both sides of the gate electrode, and a semiconductor region 14 buried in the insulation layer 16 in a region below the gate electrode. The surface scattering of the carriers and phonon scattering can be prevented while suppressing the short channel effect. Resultantly the semiconductor device can have high mobility and high speed.

摘要翻译： 半导体器件包括形成在绝缘层16上的半导体层18，形成在半导体层上的栅电极22，其间形成有栅极绝缘膜20，形成在栅极两侧的半导体层上的源/漏区24 电极，以及埋在绝缘层16内的栅极电极下方的区域的半导体区域14。 可以在抑制短通道效应的同时，防止载流子的表面散射和声子散射。 结果，半导体器件可以具有高移动性和高速度。

公开(公告)号：US20030141547A1

公开(公告)日：2003-07-31

申请号：US10345973

申请日：2003-01-17

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Katsushige Yamashita ,  Hisaji Nishimura ,  Hiromu Yamazaki ,  Masaki Inoue ,  Yoshinobu Satoh

IPC分类号： H01L021/00 ,  H01L027/12

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/84

摘要： An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.

摘要翻译： SOI半导体器件至少包括包含绝缘膜的SOI衬底和形成在绝缘膜上的半导体层; 以及形成在半导体层上的有源半导体元件。 活性半导体元件形成在由隔离区域包围的元件形成区域中，用于隔离半岛形式的岛状。 在除了形成有源半导体元件的元件形成区域之外的半导体层的一部分中形成含有高浓度杂质的吸杂层，并且在有源半导体元件的元素形成区域中不形成吸杂层 形成。

公开(公告)号：US20030104681A1

公开(公告)日：2003-06-05

申请号：US09975435

申请日：2001-10-11

发明人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC分类号： H01L021/331 ,  H01L021/8222 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L021/322 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC分类号： H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

摘要： A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

摘要翻译： 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度处形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了形成DRAM的存储电容器形成的体积为Si的深沟槽，同时在SOI上形成合并的逻辑区域的问题。

公开(公告)号：US20030089950A1

公开(公告)日：2003-05-15

申请号：US10001270

申请日：2001-11-15

发明人： Thomas F. Kuech ,  Peter D. Moran

IPC分类号： H01L027/12

CPC分类号： H01L21/76256

摘要： Silicon and silicon-germanium semiconductor-on-insulator structures are formed with strong bonds between the silicon or silicon-germanium layer and the underlying insulating substrate with low defects in the semiconductor and minimal flaws in the bonding between the semiconductor layer and the substrate. An oxide layer is initially formed on the semiconductor wafer, and the wafer may then be annealed, if necessary, to drive off water from the oxide layer so that the oxide layer is well below the water saturation of the oxide. The surfaces of the oxide layer and the substrate are then cleaned and placed into contact at relatively low temperatures to effect a strong bond. The semiconductor layer may then be thinned by mechanical or chemical processes, or both, and the completed structure annealed to perfect the bond between the semiconductor layer and the substrate.

摘要翻译： 硅和硅 - 绝缘体上半导体结构在硅或硅 - 锗层与下半导体半导体缺陷小的底层绝缘衬底之间形成强结合，并且在半导体层和衬底之间的接合中具有最小的缺陷。 首先在半导体晶片上形成氧化物层，然后如果需要，可以将晶片退火以从氧化物层排出水，使得氧化物层远低于氧化物的水饱和度。 然后将氧化物层和衬底的表面清洁并在相对低的温度下接触以实现强键。 然后可以通过机械或化学过程或两者来减薄半导体层，并且完成的结构退火以完善半导体层和衬底之间的结合。

公开(公告)号：US20030071307A1

公开(公告)日：2003-04-17

申请号：US10232700

申请日：2002-09-03

发明人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

IPC分类号： H01L029/06 ,  H01L031/0328 ,  H01L027/12 ,  H01L021/84

CPC分类号： H01L29/66742 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78684 ,  Y10S438/933

摘要： The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1nullxGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1nullxGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

公开(公告)号：US20030057495A1

公开(公告)日：2003-03-27

申请号：US10095163

申请日：2002-03-08

申请人： National University of Singapore

发明人： Hao Gong ,  Yue Wang ,  Lei Huang

IPC分类号： H01L027/01 ,  H01L027/12

CPC分类号： H01L31/1884 ,  C01G3/00 ,  C01P2002/84 ,  C01P2004/03 ,  C01P2004/04 ,  C01P2006/40 ,  C23C16/408 ,  C23C16/4481 ,  H01L31/022466 ,  Y02E10/50

摘要： This invention provides a transparent CunullAlnullO semi-conducting film having a p-type conductivity greater than 0.95null10null1 Snullcmnull1. This invention also relates to a process for preparing a CunullAlnullO film having p-type conductivity, comprising: a) controllably vaporizing organo-copper and organo-aluminum precursors and carrying the vapors into a chemical vapor deposition chamber with an inert gas flow; b)reacting and depositing the vapors on a substrate, preferably a light-transmitting substrate, through a chemical vapor deposition process.

摘要翻译： 本发明提供一种透明Cu-Al-O半导电膜，其具有大于0.95×10-1 S.cm-1的p型电导率。 本发明还涉及一种制备具有p型导电性的Cu-Al-O膜的方法，包括：a）可控地蒸发有机铜和有机铝前体，并将蒸汽携带惰性气体的化学气相沉积室 流; b）通过化学气相沉积工艺将蒸气反应并沉积在基底，优选透光基底上。

公开(公告)号：US20030052325A1

公开(公告)日：2003-03-20

申请号：US09346726

申请日：1999-07-02

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： SHOICHI MIYAMOTO ,  TOSHIAKI IWAMATSU ,  TAKASHI IPPOSHI

IPC分类号： H01L027/01 ,  H01L033/00 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L27/1203 ,  H01L29/42384

摘要： A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.

摘要翻译： 一种半导体器件，包括通过在绝缘层2上形成硅层3，在硅层3中水平布置的多个有源区3和由沟槽状构成的沟槽状形状的元件隔离部5制造的SOI衬底 绝缘体5嵌入在硅层3中的有源区域3之间，其中绝缘层2具有位于有源区域和元件隔离部分5之间的界面附近的空间6，由此可以减少固定电荷或存在的孔 在硅层和绝缘层之间的界面中的绝缘层的一侧上，在硅层的底表面上形成绝缘层的氧化过程中产生固定的电荷或空穴。

公开(公告)号：US20030042544A1

公开(公告)日：2003-03-06

申请号：US10105544

申请日：2002-03-25

申请人： Samsung Electronics Co., Ltd.

发明人： Myoung-Soo Kim

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L027/01 ,  H01L027/12

CPC分类号： H01L29/518 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/7835

摘要： The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers. The oxide pattern defines a channel region. A gate oxide layer is formed on the channel region and a gate electrode is formed to cover the channel region and to cross over the active region. The edge of the gate electrode is over the oxide pattern. A heavy doped diffusion layer is formed in the active region of both regions of a gate electrode and shallower than the lightly doped diffusion layer.

摘要翻译： 本发明包括具有浅沟槽隔离的半导体器件及其制造方法。 半导体器件包括布置成跨过有源区域的栅电极。 在有源区和栅电极的边缘之间插入氧化物图案。 氧化物图案限定栅极下方的沟道区。 在有源区域中从氧化物图案向下和向外形成轻掺杂扩散层，并且在有源区的预定区域中形成重掺杂扩散层，并被轻掺杂扩散层包围。 在制造半导体衬底的方法中，在半导体衬底的预定区域形成沟槽隔离层以限定有源区。 在一行中形成一对初步轻掺杂扩散层以跨越有源区。 然后，形成氧化物图形以至少覆盖初步轻掺杂扩散层。 氧化物图案限定了通道区域。 栅极氧化层形成在沟道区上，形成栅电极以覆盖沟道区并跨过有源区。 栅电极的边缘在氧化物图案之上。 在栅电极的两个区域的有源区中形成重掺杂的扩散层，并且比掺杂浅的扩散层浅。