公开(公告)号：US5614746A

公开(公告)日：1997-03-25

申请号：US494632

申请日：1995-06-23

申请人： Gary Hong ,  Hwi-Huang Chen

发明人： Gary Hong ,  Hwi-Huang Chen

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517

摘要： A method is provided for fabricating a split gate flash EPROM device. A stack is formed of a first dielectric layer on the lightly doped semiconductor substrate followd by a floating gate, a first intergate dielectric layer, an intermediate control gate layer, an isolating layer over the intermediate control gate layer, and a floating gate mask on the device. The stack is formed by etching in the pattern of the floating gate. A split gate mask is formed followed by ion implanting dopant into source/drain regions in the substrate adjacent to the mask with one source/drain region self aligned with the stack and the other spaced away from the other side of the stack. After mask removal, a second intergate dielectric layer blanket is formed with an etch back forming sidewalls next to the stack by etching away exposed portions of the first dielectric layer, forming a second dielectric layer on the substrate and the source/drain regions. Removal of the isolating layer over the intermediate control gate layer follows. Then a blanket control gate layer over the device and a control gate mask are formed, patterning the control gate layer by etching portions of the control gate layer unprotected by the control gate mask, and removal of the control gate mask.

摘要翻译： 提供了一种用于制造分离栅闪光EPROM器件的方法。 堆叠由轻掺杂半导体衬底上的第一介电层形成，后面是浮栅，第一栅间电介质层，中间控制栅层，中间控制栅极层上的隔离层，以及浮置栅极上的浮栅掩模 设备。 堆叠通过在浮动栅极的图案中进行蚀刻而形成。 形成分裂栅掩模，随后将离子注入掺杂剂注入到与掩模相邻的衬底中的源极/漏极区域中，其中一个源极/漏极区域与堆叠自对准，而另一个源极/漏极区域与叠层的另一侧间隔开。 在去除掩模之后，通过蚀刻掉第一介电层的暴露部分，在衬底和源极/漏极区上形成第二电介质层，形成第二间隔栅电介质层毯，其中蚀刻形成靠近堆叠的侧壁。 遵循中间控制栅极层上的隔离层的去除。 然后形成器件上的覆盖层控制栅极层和控制栅极掩模，通过蚀刻由控制栅极掩模保护的控制栅极层的部分以及去除控制栅极掩模来图案化控制栅极层。

公开(公告)号：US5612915A

公开(公告)日：1997-03-18

申请号：US591390

申请日：1996-01-25

申请人： Stephen Fu ,  Hsin-Li Chen

发明人： Stephen Fu ,  Hsin-Li Chen

IPC分类号： G11C7/12 ,  G11C11/34

CPC分类号： G11C7/12

摘要： A clamp circuit for a read-only-memory (ROM) device provides clamp voltages which can uniformly compensate for the parasitic capacitance on ROM word lines and improve the performance of the ROM device. The clamp circuit includes an active load, a plurality of amplifiers and a transmission gate. The amplifiers have various trip voltages and are controlled by different decoding signals for providing various clamp voltages to different word lines in the ROM device. Each amplifier is composed of a NOR gate and a transistor. The amplifier trip voltages can be easily set to desired values when designing NOR gate layout patterns without additional complicated processes being introduced into the fabrication methodology of a semiconductor integrated circuit.

摘要翻译： 用于只读存储器（ROM）器件的钳位电路提供钳位电压，其可以均匀地补偿ROM字线上的寄生电容并且提高ROM器件的性能。 钳位电路包括有源负载，多个放大器和传输门。 放大器具有各种跳闸电压，并且由不同的解码信号控制，以向ROM器件中的不同字线提供各种钳位电压。 每个放大器由或非门和晶体管组成。 当设计NOR门布局图案时，放大器跳闸电压可以很容易地设置为所需的值，而不会在半导体集成电路的制造方法中引入额外的复杂工艺。

公开(公告)号：US5612239A

公开(公告)日：1997-03-18

申请号：US519069

申请日：1995-08-24

申请人： Jengping Lin ,  Sun-Chieh Chien

发明人： Jengping Lin ,  Sun-Chieh Chien

IPC分类号： H01L21/316 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/316

摘要： A process for manufacturing an LDD type of FET, based on the salicide process, is described. Said process does not lead to short circuits between the drain region and and the main body of the FET through the buried contact. The process is based on the use of Liquid Phase Deposition (LPD) as the method for growing the oxide layer from which the spacers are formed. Since oxide layers formed through LPD will deposit preferentially on silicon and silicon oxide surfaces relative to photoresist surfaces, the areas in which the LPD layer forms are readily controlled. This feature allows the buried contact layer to be replaced by an extended drain region which can be connected to other parts of the integrated circuit (by the salicide process) without the danger of shorting paths being formed therein.

摘要翻译： 描述了基于自对准硅化物工艺制造LDD型FET的工艺。 所述工艺不会通过埋入触点而导致漏极区域和FET主体之间的短路。 该方法基于使用液相沉积（LPD）作为生长形成间隔物的氧化物层的方法。 由于通过LPD形成的氧化物层相对于光致抗蚀剂表面优先沉积在硅和氧化硅表面上，因此容易控制LPD层形成的区域。 该特征允许掩埋接触层被延伸的漏极区域替代，该漏极区域可以连接到集成电路的其它部分（通过自对准硅化物工艺），而不会在其中形成短路路径的危险。

公开(公告)号：US5611448A

公开(公告)日：1997-03-18

申请号：US533661

申请日：1995-09-25

申请人： Fu-Liang Chen

发明人： Fu-Liang Chen

IPC分类号： H01L21/673 ,  B65D85/00

CPC分类号： H01L21/67373 ,  H01L21/67386

摘要： An integrated circuit wafer protective container for containing IC wafers during the process of IC wafer fabrication is disclosed. The protective container comprises a wafer-containing member and a wafer-protecting and securing member. The wafer-containing member is of a substantially cylindrical shape of a tube having a closed end and an open end. The inner diameter of the wafer-containing member is suitable for containing the IC wafers. The wafer-protecting and securing member is of a substantially cylindrical shape of a tube having a closed end and open end. The inner diameter of the wafer-protecting and securing member is suitable for receiving the cylindrical body of the wafer-containing member. The wafer-protecting and securing member has a number of latching protrusions formed at its open end on the inner side wall of its cylindrical shaped tube. The wafer-containing member has a number of latching slots formed at its closed end on the exterior surface of its cylindrical shaped tube. Each of the latching protrusions mates with a corresponding one of latching slots when the cylindrical body of the wafer-containing member is fully received inside the wafer-protecting and securing member. A wafer confinement member secures a stack of IC wafers stored in the wafer containing member.

摘要翻译： 公开了一种用于在IC晶片制造过程中容纳IC晶片的集成电路晶片保护容器。 保护容器包括含晶片的构件和晶片保护和固定构件。 含晶片的构件是具有封闭端和开口端的管的基本上圆柱形的形状。 含晶片的构件的内径适于容纳IC晶片。 晶片保护和固定构件具有具有封闭端和开口端的管的大致圆柱形形状。 晶片保护和固定构件的内径适于接收含晶片的构件的圆柱体。 晶片保护和固定构件具有在其圆柱形管的内侧壁上的开口端处形成的多个闭锁突起。 含晶片的构件具有在其圆柱形管的外表面上的封闭端处形成的多个闩锁槽。 当晶片容纳构件的圆柱体完全容纳在晶片保护和固定构件内部时，每个闩锁突起与相应的一个闩锁槽配合。 晶片限制构件固定存储在晶片容纳构件中的一堆IC晶片。

公开(公告)号：US5610743A

公开(公告)日：1997-03-11

申请号：US549866

申请日：1995-10-30

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： G02F1/1337

CPC分类号： G02F1/133753

摘要： A liquid crystal display having an improved angular distribution for emerging radiation is described, together with a method for manufacturing it. This was achieved by forming patterns, one per pixel, of concentric annuli in one of the orientation layers and radial spokes in the other orientation layer. This guarantees that there is a wide range in the orientations of the twisted nematics, leading to an improved angular distribution for the emerging radiation. The invention is applicable to both monochrome as well as color displays and may also be used as a way to adjust, during manufacturing, the angular distribution of the emerging light.

摘要翻译： 描述具有改进的辐射辐射角分布的液晶显示器及其制造方法。 这是通过在另一个取向层中的一个取向层和径向辐条中形成同心圆环的每像素一个图案来实现的。 这确保了扭转线性方向的范围很广，导致新兴辐射角度分布的改善。 本发明可应用于单色和彩色显示器，并且还可以用作在制造期间调整出现的光的角度分布的一种方式。

公开(公告)号：US5585303A

公开(公告)日：1996-12-17

申请号：US608104

申请日：1996-02-28

申请人： Gary Hong ,  J. S. Jason Jenq

发明人： Gary Hong ,  J. S. Jason Jenq

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for manufacturing a DRAM capacitor on a substrate in which an insulator, a first barrier layer, a first conductive layer and a second barrier layer are sequentially applied over the gate electrode and source/drain areas of the substrate. Portions of the deposited layers above the source/drain areas are removed to form trenches which reach these areas. After portions of the second barrier layer and the first conductive layer are etched away, a conductive material layer is deposited thereover, an n-type dopant is doped into the conductive material layer, the dopant is diffused into the substrate to form n.sup.+ -type diffused regions, and the conductive material layer is shaped to form spaced-apart poly spacers and poly fins. Thereafter the first and the second barrier layers are removed to form a bottom plate of the DRAM capacitor which is defined by the first conductive layer, the poly spacers and the poly fins. Finally, a dielectric film is applied over the bottom plate and a further conductive layer is deposited thereover so that it forms a top plate of the DRAM capacitor. The resulting stack/trench capacitor has a larger dielectric film area and a correspondingly larger capacitance.

摘要翻译： 一种用于在衬底上制造DRAM电容器的方法，其中绝缘体，第一势垒层，第一导电层和第二阻挡层依次施加在衬底的栅极电极和源极/漏极区域上。 在源极/漏极区域上方的沉积层的部分被去除以形成到达这些区域的沟槽。 在第二阻挡层和第一导电层的部分被蚀刻掉之后，在其上沉积导电材料层，将n型掺杂剂掺杂到导电材料层中，掺杂剂扩散到衬底中以形成n +型扩散 区域，并且导电材料层被成形为形成间隔开的聚间隔物和多个翅片。 此后，去除第一和第二阻挡层以形成DRAM电容器的底板，其由第一导电层，多隔板和多个鳍片限定。 最后，将电介质膜施加在底板上，并在其上沉积另外的导电层，从而形成DRAM电容器的顶板。 所得到的堆叠/沟槽电容器具有较大的电介质膜面积和相应较大的电容。

公开(公告)号：US5585299A

公开(公告)日：1996-12-17

申请号：US617600

申请日：1996-03-19

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/8238

CPC分类号： H01L27/088 ,  H01L21/823443 ,  H01L27/0251 ,  H01L27/0266

摘要： Disclosed is a process for fabricating a semiconductor device having both a functional region and an electrostatic discharge (ESD) protective region formed on the same substrate. A gate oxide layer is formed on both the functional region and the ESD protective region and a polysilicon layer is formed on the gate oxide layer. A mask is used to etch the polysilicon layer and the gate oxide layer to form gate electrode and also expose part of the silicon substrate. Ions are implanted to form a lightly doped source/drain electrode. An ESD mask is used to selectively remove part of the oxide layer on the functional region, thus forming an isolator on lateral sides of the gate electrode in the functional region. Ions are then implanted to form a heavily doped region and lightly doped source/drain electrode. After that, a metallization layer is formed by sputtering deposition and then rapid thermal annealing and etching are performed to form self-aligning TiSi.sub.2 layer on the gate electrode and on exposed surface of the source/drain electrode. Then the ESD mask is used again to selectively remove part of the oxide layer on the ESD protective region. Finally, ions are implanted to form a heavily doped region. Using the same ESD mask to construct both the ESD protective region and the functional region provides considerable cost savings.

摘要翻译： 公开了一种制造具有形成在同一基板上的功能区域和静电放电（ESD）保护区域的半导体器件的方法。 在功能区域和ESD保护区域上形成栅极氧化层，在栅极氧化物层上形成多晶硅层。 使用掩模来蚀刻多晶硅层和栅极氧化物层以形成栅电极并且还暴露部分硅衬底。 植入离子以形成轻掺杂的源/漏电极。 使用ESD掩模来选择性地去除功能区域上的氧化物层的一部分，从而在功能区域中的栅电极的侧面上形成隔离器。 然后将离子注入以形成重掺杂区域和轻掺杂源极/漏电极。 之后，通过溅射沉积形成金属化层，然后进行快速热退火和蚀刻，以在栅电极和源极/漏电极的暴露表面上形成自对准TiSi 2层。 然后再次使用ESD掩模以选择性地去除ESD保护区域上的氧化物层的一部分。 最后，注入离子以形成重掺杂区域。 使用相同的ESD掩模构建ESD保护区域和功能区域可大大节省成本。

公开(公告)号：US5585296A

公开(公告)日：1996-12-17

申请号：US599923

申请日：1996-02-12

申请人： Cheng-Hui Chung ,  Yi-Chung Sheng ,  Belle Chia

发明人： Cheng-Hui Chung ,  Yi-Chung Sheng ,  Belle Chia

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/265

CPC分类号： H01L27/11253 ,  H01L27/112 ,  Y10S438/981

摘要： A method of fabricating memory cells with buried bit lines. In this method, a pad oxide layer is formed on a first conductivity-type silicon substrate. A photoresist layer is formed on the pad oxide layer while exposing predetermined areas of channels. A thick oxide layer is deposited by liquid phase deposition (LPD). The photoresist layer is removed. Second conductivity-type impurities are implanted to form source-drain electrodes using the thick oxide layer as a mask. The thick oxide layer and the pad oxide layer are removed to form bit lines and then word lines are formed crossing the bit lines, whereby the structure with buried bit lines and an array of memory cells is completed.

摘要翻译： 一种制造具有掩埋位线的存储单元的方法。 在该方法中，在第一导电型硅衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成光致抗蚀剂层，同时暴露预定区域的通道。 通过液相沉积（LPD）沉积厚的氧化物层。 去除光致抗蚀剂层。 注入第二导电型杂质以使用厚氧化物层作为掩模形成源 - 漏电极。 去除厚氧化物层和焊盘氧化物层以形成位线，然后形成与位线交叉的字线，由此完成具有掩埋位线和存储器单元阵列的结构。

公开(公告)号：US5578857A

公开(公告)日：1996-11-26

申请号：US349432

申请日：1994-12-05

申请人： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

IPC分类号： H01L21/8246 ,  H01L29/76

CPC分类号： H01L27/1126

摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

摘要翻译： 根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。 特别地，减小字线间距以在垂直于字线的方向上增加单元密度。 本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

公开(公告)号：US5576238A

公开(公告)日：1996-11-19

申请号：US490787

申请日：1995-06-15

申请人： Chien-Chih Fu

发明人： Chien-Chih Fu

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： A process for fabricating memory cells of a static random access memory (SRAM) device is disclosed to reduce the required die area and increase storage capacity. Each of the memory cells of the SRAM comprises a group of four MOS transistors, a pair of resistors, a pair of bit lines, as well as a word line. The process of fabrication the memory cells of the SRAM device comprises a number of process steps that are implemented subsequently on the surface of said semiconductor substrate, with the first and second MOS transistors first formed on the semiconductor substrate. According to the process, the first and second resistors are then formed on top of the first and second MOS transistors. Then the third and fourth MOS transistors and a word line are subsequently formed on top of the first and second resistors. Finally, the first and second bit lines for the memory cells are formed on top of the third and fourth MOS transistors. The process for fabricating the memory cells is characterized by the fact that the third and fourth MOS transistors are fabricated as vertical conduction transistors having their drains, sources and gates aligned substantially in a direction orthogonal to the plane of the semiconductor substrate.

摘要翻译： 公开了一种用于制造静态随机存取存储器（SRAM）器件的存储单元的过程，以减少所需的管芯面积并增加存储容量。 SRAM的每个存储单元包括一组四个MOS晶体管，一对电阻器，一对位线以及字线。 制造SRAM器件的存储单元的过程包括随后在所述半导体衬底的表面上实施的多个工艺步骤，其中第一和第二MOS晶体管首先形成在半导体衬底上。 根据该过程，第一和第二电阻器然后形成在第一和第二MOS晶体管的顶部。 然后在第一和第二电阻器的顶部随后形成第三和第四MOS晶体管和字线。 最后，存储单元的第一和第二位线形成在第三和第四MOS晶体管的顶部。 用于制造存储单元的工艺的特征在于，第三和第四MOS晶体管被制造为垂直导电晶体管，其垂直导电晶体管的漏极，源极和栅极基本上在与半导体衬底的平面正交的方向上排列。