公开(公告)号：US07727393B2

公开(公告)日：2010-06-01

申请号：US10593480

申请日：2005-04-06

Applicant: Kwang Jin Lee ,  Moo Seok Lee ,  Yong Cheol Shin ,  Seong Hak Choi ,  Young Tai Woo

Inventor： Kwang Jin Lee ,  Moo Seok Lee ,  Yong Cheol Shin ,  Seong Hak Choi ,  Young Tai Woo

IPC: B01D63/02 ,  B01D61/00

CPC classification number: B01D63/02 ,  B01D61/18 ,  B01D63/026 ,  B01D65/08 ,  B01D2313/06 ,  B01D2313/08 ,  B01D2315/06 ,  B01D2321/185 ,  C02F1/444

Abstract: Disclosed is a submerged hollow fiber membrane module which is easy to expand, has a small installation area, and exhibits excellent contamination prevention and durability. The submerged hollow fiber membrane module comprises: (I) a module body divided into two portions which has a permeated water collection space (5) and a permeated water outlet (3); (II) module support tubes (17) which are vertically connected to the upper and lower ends of the module body; (III) a plate type module header insertion layer which is provided with hollow fiber membrane spaces (10), and is inserted into the module body; (IV) a plate type diffusion layer which is provided with a diffusion port (4) and diffusion tubes (11) and is inserted into the module body subsequent to the module header insertion layer; and (V) module headers which are inserted into the module header insertion layer.

Abstract translation: 公开了一种容易膨胀，安装面积小，防污染性和耐久性优异的浸没式中空纤维膜组件。 浸没式中空纤维膜组件包括：（I）分为两部分的模块体，其具有渗透水收集空间（5）和渗透水出口（3）; （II）模块支撑管（17），其垂直连接到模块主体的上端和下端; （III）板型模块插头层，其设置有中空纤维膜空间（10），并插入模块体内; （IV）板式扩散层，其具有扩散口（4）和扩散管（11），并在模块插入层之后插入模块主体中; 和（V）模块插头插入模块插头层。

公开(公告)号：US20100008133A1

公开(公告)日：2010-01-14

申请号：US12559792

申请日：2009-09-15

Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C7/10 ,  G11C7/06 ,  G11C7/00

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.

Abstract translation: 在相变存储器中写入数据的方法包括： 接收要写入所述多个相变存储单元中的所选择的相变存储单元的写入数据，感测存储在所选择的相变存储单元中的数据，确定所感测的数据是否等于写入数据，以及如果 感测数据不等于写数据，对所选择的相变存储单元迭代地施加写入电流，其中相变存储单元的电阻状态根据与写入电流的电平相对应的热量而改变， 写入电流在连续的迭代应用程序之间改变。

公开(公告)号：US20090321344A1

公开(公告)日：2009-12-31

申请号：US12486112

申请日：2009-06-17

Applicant: Kwang-Jin LEE ,  Moo-Seok LEE ,  Yong-Cheol SHIN

Inventor： Kwang-Jin LEE ,  Moo-Seok LEE ,  Yong-Cheol SHIN

IPC: B01D63/00 ,  B01D35/30

CPC classification number: B01D63/02 ,  B01D2313/21

Abstract: A header for filtering membrane module and a filtering membrane module using the same is disclosed, which is capable of maximizing efficiency in power consumption by securing a constant flow of permeate through the use of a relatively-low negative pressure, the header for filtering membrane module comprising a body with a permeate collecting space therein; and a conduit at one end of the body, the conduit being in fluid communication with the permeate collecting space, wherein at least a portion of the permeate collecting space has an inclined shape.

Abstract translation: 公开了用于过滤膜组件的头部和使用其的过滤膜组件，其能够通过使用相对低的负压确保渗透物的恒定流量来最大化功率消耗的效率，用于过滤膜组件 包括其中具有渗透物收集空间的主体; 以及在所述主体的一端处的导管，所述导管与所述渗透物收集空间流体连通，其中所述渗透物收集空间的至少一部分具有倾斜形状。

公开(公告)号：US20090161421A1

公开(公告)日：2009-06-25

申请号：US12395999

申请日：2009-03-02

Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C11/416

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

公开(公告)号：US07535760B2

公开(公告)日：2009-05-19

申请号：US11902424

申请日：2007-09-21

Applicant: Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

Inventor： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

IPC: G11C14/00

CPC classification number: H01L27/10802 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4063 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

Abstract translation: 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

公开(公告)号：US07535747B2

公开(公告)日：2009-05-19

申请号：US11844512

申请日：2007-08-24

Applicant: Kwang-jin Lee ,  Woo-yeong Cho

Inventor： Kwang-jin Lee ,  Woo-yeong Cho

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078

Abstract: In a phase change random access memory (PRAM) device, data is programmed in selected memory cells using a plurality of program loops. In each program loop, division program operations for cell groups including the selected memory cells are performed in consecutive timeslots.

Abstract translation: 在相变随机存取存储器（PRAM）装置中，使用多个程序循环将数据编程在所选存储单元中。 在每个程序循环中，在连续的时隙中执行包括所选存储单元的单元组的分割程序操作。

公开(公告)号：US07529124B2

公开(公告)日：2009-05-05

申请号：US11727711

申请日：2007-03-28

Applicant: Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

Inventor： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

公开(公告)号：US07486536B2

公开(公告)日：2009-02-03

申请号：US11301322

申请日：2005-12-12

Applicant: Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

Inventor： Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Disclosed is a phase-changeable memory device and method of programming the same. The phase-changeable memory device includes memory cells each having multiple states, and a program pulse generator providing current pulses to the memory cells. The program pulse generator initializes a memory cell to a reset or set state by applying a first pulse thereto and thereafter provides a second pulse to program the memory cell to one of the multiple states. According to the invention, as a memory cell is programmed after being initialized to a reset or set state, it is possible to correctly program the memory cell without influence from the previous state of the memory cell.

Abstract translation: 公开了一种可变相存储器件及其编程方法。 相位可变存储器件包括各自具有多个状态的存储单元，以及向存储单元提供电流脉冲的编程脉冲发生器。 程序脉冲发生器通过向其施加第一个脉冲而将存储单元初始化为复位或置位状态，此后提供第二脉冲以将存储器单元编程为多个状态之一。 根据本发明，由于在初始化为复位或置位状态之后对存储单元进行编程，所以可以在不影响存储单元的先前状态的情况下正确编程存储单元。

公开(公告)号：US20080112220A1

公开(公告)日：2008-05-15

申请号：US11984145

申请日：2007-11-14

Applicant: Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

Inventor： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

Abstract translation: 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

公开(公告)号：US20080056023A1

公开(公告)日：2008-03-06

申请号：US11834843

申请日：2007-08-07

Applicant: Kwang-jin LEE ,  Choong-keun KWAK ,  Du-eung KIM

Inventor： Kwang-jin LEE ,  Choong-keun KWAK ,  Du-eung KIM

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

Abstract: In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

Abstract translation: 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。