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公开(公告)号：US06850455B2
公开(公告)日：2005-02-01
申请号：US10330965
申请日：2002-12-26
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77
摘要： Providing a multiplexor outputting a reference voltage on unselected lines. A multiplexor that has at least one selected line and multiple unselected lines will have the unselected lines at a reference voltage. The selected line allows at least a portion of voltage to pass. Two gate circuits are used for each line, one that controls whether voltage (or a portion thereof) will pass, the other that connects the first gate circuit to a reference voltage, such as ground. In some embodiments the second gate circuit is always on, but is relatively small, such that the connection to the reference voltage has a weak effect on the output voltage. In other embodiments, the second gate circuit is only on when its associated first gate circuit is off.
摘要翻译： 提供在未选择的线路上输出参考电压的多路复用器。 具有至少一个选定行和多个未选择行的多路复用器将使未选择的行处于参考电压。 所选择的线路允许至少一部分电压通过。 每条线使用两个门电路，一个控制电压（或其一部分）是否通过，另一个将第一门电路连接到参考电压，例如接地。 在一些实施例中，第二栅极电路总是导通，但是相对较小，使得与参考电压的连接对输出电压具有较弱的影响。 在其他实施例中，第二门电路仅在其相关联的第一门电路断开时导通。
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公开(公告)号：US06836421B2
公开(公告)日：2004-12-28
申请号：US10613099
申请日：2003-07-01
IPC分类号： G11C502
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuit.
摘要翻译： 适合指定线路间距的线路驱动器。 将线驱动器完全放置在交叉点阵列下方的一种方法需要将线驱动器向上分开，使得线驱动器的一部分位于交叉点阵列的第一侧，而另一部分在相对侧。 然而，使用这种技术要求驱动器的宽度不大于被驱动的存储单元的宽度。 这可以通过堆叠晶体管来实现，使得线路驱动器配合在指定的线间距内，但是必须包括所有必要的电路。
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公开(公告)号：US08569160B2
公开(公告)日：2013-10-29
申请号：US13665603
申请日：2012-10-31
申请人： Darrell Rinerson , Robin Cheung
发明人： Darrell Rinerson , Robin Cheung
IPC分类号： H01L21/768
CPC分类号： G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
摘要： Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.
摘要翻译： 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。
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公开(公告)号：US20130059436A1
公开(公告)日：2013-03-07
申请号：US13665603
申请日：2012-10-31
申请人： Darrell Rinerson , Robin Cheung
发明人： Darrell Rinerson , Robin Cheung
IPC分类号： H01L21/768
CPC分类号： G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
摘要： Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.
摘要翻译： 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。
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125.发明申请Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory 审中-公开集成电路包括四层垂直堆叠嵌入式可重写非易失性双端存储器公开(公告)号：US20110080767A1
公开(公告)日：2011-04-07
申请号：US12928239
申请日：2010-12-06
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.
摘要翻译： 公开了一种整体形成在包括有源电路的基板的顶部上的多层非易失性存储器。 每层存储器包括具有多电阻状态材料层的存储器单元（例如，两端存储单元），其在存储单元上施加写入电压时在低电阻状态和高电阻状态之间改变其电阻状态 。 可以通过在存储器单元上施加读取电压来非存储性地确定存储单元中存储的数据。 数据存储容量可以通过增加或减少在衬底上整体制造的存储层的数量（例如，四层以上或者四层以下）来适应特定应用。 存储器单元可以包括仅在读取和写入操作期间允许访问存储器单元的非欧姆器件。 每个存储器层可以包括交叉点阵列。
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公开(公告)号：US20100159688A1
公开(公告)日：2010-06-24
申请号：US12454322
申请日：2009-05-15
申请人： Darrell Rinerson , Robin Cheung
发明人： Darrell Rinerson , Robin Cheung
IPC分类号： H01L21/768
CPC分类号： G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
摘要： Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.
摘要翻译： 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。
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公开(公告)号：US07457147B2
公开(公告)日：2008-11-25
申请号：US11707340
申请日：2007-02-16
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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128.发明授权Method for two-cycle sensing in a two-terminal memory array having leakage current 有权具有漏电流的双端存储器阵列中的双周期感测方法公开(公告)号：US07436723B2
公开(公告)日：2008-10-14
申请号：US12074448
申请日：2008-03-03
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C13/004 , G11C2013/0057
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译： 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。
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公开(公告)号：US07382645B2
公开(公告)日：2008-06-03
申请号：US11809643
申请日：2007-06-01
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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公开(公告)号：US07227767B2
公开(公告)日：2007-06-05
申请号：US11446733
申请日：2006-06-05
IPC分类号： G11C5/02
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.
摘要翻译： 具有快速访问时间的交叉点阵列。 交叉点阵列由半导体衬底上的驱动器驱动。 可以定位用于单层交叉点阵列或堆叠交叉点阵列的底层的驱动程序，以改善访问时间。 具体地，如果x方向驱动器位于x方向导电阵列线的中间，并且y方向驱动器位于y方向导电阵列线的中间，则存取时间将被改善。
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