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    Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory
    1.
    发明申请
    Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory 审中-公开
    集成电路包括四层垂直堆叠嵌入式可重写非易失性双端存储器

    公开(公告)号：US20110080767A1

    公开(公告)日：2011-04-07

    申请号：US12928239

    申请日：2010-12-06

    申请人： Darrell Rinerson ,  Christoophe J. Chevallier ,  Steve Kuo-Ren Hsia

    发明人： Darrell Rinerson ,  Christoophe J. Chevallier ,  Steve Kuo-Ren Hsia

    IPC分类号： G11C11/00

    CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    摘要： A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.

    摘要翻译： 公开了一种整体形成在包括有源电路的基板的顶部上的多层非易失性存储器。 每层存储器包括具有多电阻状态材料层的存储器单元（例如，两端存储单元），其在存储单元上施加写入电压时在低电阻状态和高电阻状态之间改变其电阻状态 。 可以通过在存储器单元上施加读取电压来非存储性地确定存储单元中存储的数据。 数据存储容量可以通过增加或减少在衬底上整体制造的存储层的数量（例如，四层以上或者四层以下）来适应特定应用。 存储器单元可以包括仅在读取和写入操作期间允许访问存储器单元的非欧姆器件。 每个存储器层可以包括交叉点阵列。

    Conductive memory stack with non-uniform width
    5.
    发明授权
    Conductive memory stack with non-uniform width 有权
    具有不均匀宽度的导电存储器堆叠

    公开(公告)号：US07439082B2

    公开(公告)日：2008-10-21

    申请号：US11369663

    申请日：2006-03-06

    申请人： Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

    发明人： Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

    IPC分类号： H01L21/8242

    CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

    摘要翻译： 提供导电存储器堆叠。 存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。 底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面 第四表面积。 多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。 此外，第四表面积不等于第二表面积。