公开(公告)号：US20140345517A1

公开(公告)日：2014-11-27

申请号：US13901298

申请日：2013-05-23

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: C30B23/04 ,  G02B6/13 ,  G02B6/12 ,  C30B25/04 ,  C30B29/06

CPC classification number: G02B6/107 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/032 ,  G02B6/122 ,  G02B6/131 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract translation: 在非牺牲半导体材料衬底层的顶部上形成牺牲半导体材料条。 外延生长非牺牲半导体材料的保形层以覆盖基底层和牺牲半导体材料条。 执行蚀刻以选择性地去除牺牲半导体材料条并留下被保形层和基底层包围的中空通道。 使用退火，共形层和基底层被回流以产生包括中空通道的光波导结构。

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140312461A1

公开(公告)日：2014-10-23

申请号：US13866077

申请日：2013-04-19

Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/761 ,  H01L29/06

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。

公开(公告)号：US08860123B1

公开(公告)日：2014-10-14

申请号：US13852720

申请日：2013-03-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/792 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140099769A1

公开(公告)日：2014-04-10

申请号：US13647986

申请日：2012-10-09

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORP.

Inventor： Nicolas Loubet ,  Qing Liu ,  Shom Ponoth

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/31111 ,  H01L21/76232 ,  H01L21/84

Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.

Abstract translation: 通过将衬底上的掩埋氧化物覆盖在衬底中以及通过有源硅层上的任何焊盘电介质的有源硅层蚀刻隔离沟槽。 有源硅层的横向外延生长在隔离沟槽中形成至少约5纳米的横向距离的突起，并且围绕突起的部分隔离沟槽被电介质填充。 在包括电介质的有源硅层的部分上形成凸起的源极/漏极区。 结果，穿过凸起的源极/漏极区域的边缘的不对准触点保持与隔离沟槽中的衬底的侧壁间隔开。

公开(公告)号：US11069682B2

公开(公告)日：2021-07-20

申请号：US16751036

申请日：2020-01-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/8234

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US10700194B2

公开(公告)日：2020-06-30

申请号：US16026663

申请日：2018-07-03

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20190081079A1

公开(公告)日：2019-03-14

申请号：US16180223

申请日：2018-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US10163684B2

公开(公告)日：2018-12-25

申请号：US15831761

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Bruce Doris ,  Hong He ,  Qing Liu

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.