中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

136 records (took 0.022 seconds)

    INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY
    123.
    发明申请
    INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY 有权

    公开(公告)号：US20210343635A1

    公开(公告)日：2021-11-04

    申请号：US17375360

    申请日：2021-07-14

    Applicant: Intel Corporation

    Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

    IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

    INTERCONNECT STACK WITH LOW-K DIELECTRIC
    124.
    发明申请
    INTERCONNECT STACK WITH LOW-K DIELECTRIC 有权

    公开(公告)号：US20210287979A1

    公开(公告)日：2021-09-16

    申请号：US16817309

    申请日：2020-03-12

    Applicant: Intel Corporation

    Inventor： Veronica Aleman Strong ,  Henning Braunisch ,  Hiroki Tanaka ,  Haobo Chen

    IPC: H01L23/498

    Abstract: Embodiments may relate to a microelectronic package with an interconnect stack that includes a cavity therein. The cavity may include a dielectric material with a dielectric value less than 3.9. The microelectronic package may further include first and second conductive elements in the cavity, with the dielectric material positioned therebetween. Other embodiments may be described or claimed.

    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE
    125.
    发明申请
    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 有权

    公开(公告)号：US20210057345A1

    公开(公告)日：2021-02-25

    申请号：US17091657

    申请日：2020-11-06

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    High density interconnect structures configured for manufacturing and performance
    127.
    发明授权
    High density interconnect structures configured for manufacturing and performance 有权

    公开(公告)号：US10833020B2

    公开(公告)日：2020-11-10

    申请号：US16305752

    申请日：2016-06-30

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Patent Agency Ranking