公开(公告)号：US10539884B2

公开(公告)日：2020-01-21

申请号：US15902036

申请日：2018-02-22

Applicant: International Business Machines Corporation

Inventor： Luciana Meli Thompson ,  Ashim Dutta ,  Ekmini A. De Silva

IPC: G01R31/26 ,  G03F7/20 ,  G03F7/16 ,  C23C16/455 ,  C23C16/24 ,  C23C16/40 ,  H01L21/027 ,  H01L21/02 ,  H01L21/66 ,  H01J37/28

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic EUV sensitive photoresists generally includes conformal deposition of a silicon derivative or a metal oxide onto the relief image, wherein the silicon derivative is a material selected to have a dielectric constant that is greater than the dielectric constant of the underlying organic EUV sensitive photoresist. The conformal deposition of the silicon derivative or the metal oxide includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers.

公开(公告)号：US20250125285A1

公开(公告)日：2025-04-17

申请号：US18486526

申请日：2023-10-13

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Brandon Noland Canedy

IPC: H01L23/62 ,  H01H69/02 ,  H01H85/02 ,  H01H85/044

Abstract: An electrical fuse for an integrated circuit (IC). The electrical fuse includes a dielectric material substrate, and at least one line of conducting material located in the dielectric material substrate. Each of the at least one line of conducting material includes a first conductive structure, a second conductive structure, and a fuse element extending horizontally between the first and second conductive structures. The fuse element has a height that is less than the height of the first and second conductive structures.

公开(公告)号：US12272545B2

公开(公告)日：2025-04-08

申请号：US16824559

申请日：2020-03-19

Applicant: International Business Machines Corporation

Inventor： Devika Sil ,  Ashim Dutta ,  Yann Mignot ,  John Christopher Arnold ,  Daniel Charles Edelstein ,  Kedari Matam ,  Cornelius Brown Peethala

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/3065

Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

公开(公告)号：US20250096125A1

公开(公告)日：2025-03-20

申请号：US18470472

申请日：2023-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Kishan Jayanand

IPC: H01L23/525

Abstract: A horizontal antifuse structure including a fuse dielectric layer, two slanted annular metal structures arranged adjacent to and opposite one another, wherein bottom portions of the two slanted annular metal structures are embedded in the fuse dielectric layer.

公开(公告)号：US20250096123A1

公开(公告)日：2025-03-20

申请号：US18468758

申请日：2023-09-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Shravana Kumar Katakam

IPC: H01L23/525

Abstract: A antifuse structure including a first metal sidewall spacer and a second metal sidewall spacer arranged on opposite sides of a tapered dielectric pedestal, and a fuse dielectric on top of the tapered dielectric pedestal and between the first metal sidewall spacer and the second metal sidewall spacer.

公开(公告)号：US20240324469A1

公开(公告)日：2024-09-26

申请号：US18186230

申请日：2023-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SON NGUYEN ,  Ashim Dutta ,  Rudy J. Wojtecki

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, a dielectric encapsulation layer surrounding vertical side surfaces of the MTJ stack, a metal encapsulation layer surrounding an upper horizontal surface and a portion of a vertical side surface of the dielectric encapsulation layer, and a dielectric surrounding a remaining portion of the vertical side surface of the dielectric encapsulation layer. A method including method includes forming a magnetic tunnel junction (MTJ) stack, forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack, and forming a metal encapsulation layer surrounding an upper horizontal surface and a portion of a vertical side surface of the dielectric encapsulation layer.

公开(公告)号：US11923311B2

公开(公告)日：2024-03-05

申请号：US17737212

申请日：2022-05-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538

CPC classification number: H01L23/5386 ,  H01L21/76838 ,  H01L23/53228 ,  H01L23/53257

Abstract: An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.

公开(公告)号：US11910722B2

公开(公告)日：2024-02-20

申请号：US17542696

申请日：2021-12-06

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: G11C11/16 ,  H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure.

公开(公告)号：US11830807B2

公开(公告)日：2023-11-28

申请号：US17499123

申请日：2021-10-12

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Dominik Metzler ,  John Arnold

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5283

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

公开(公告)号：US11699592B2

公开(公告)日：2023-07-11

申请号：US17467428

申请日：2021-09-06

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

IPC: H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.