公开(公告)号：US20230187342A1

公开(公告)日：2023-06-15

申请号：US17547669

申请日：2021-12-10

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  PRASAD BHOSALE ,  Alexander Edward Hess ,  SON NGUYEN ,  Rudy J. Wojtecki

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L23/5226 ,  H01L21/76897 ,  H01L21/76879 ,  H01L21/31053 ,  H01L21/76883

Abstract: A method of forming a fully-aligned via (FAV) structure is provided. The method includes arranging conductive material adjacent to a dielectric pad and chemically deactivating a surface of the conductive material by forming a dopant-free surface-aligned monolayer (SAM) thereon. Dielectric material is deposited onto the dielectric pad aside the dopant-free SAM and the dopant-free SAM is removed from the surface of the conductive material.

公开(公告)号：US20240222278A1

公开(公告)日：2024-07-04

申请号：US18147731

申请日：2022-12-29

Applicant: International Business Machines Corporation

Inventor： Takeshi Nogami ,  SON NGUYEN ,  Cornelius Brown Peethala

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76879 ,  H01L23/53209 ,  H01L23/5329

Abstract: An integrated circuit configuration with graphene coated metal interconnect structures and airgap structures between the graphene coated metal interconnect structures and method for fabrication of the integrated circuit configuration may be provided. The structure may include a metal interconnect structure in contact with an electrode upon a substrate fabricated through subtractive metal reactive ion etching. The metal interconnect structure may have a thin coating of hydrophobic graphene surrounding the exterior of the metal interconnect structure to prevent oxidation of the metal interconnect and to prevent parasitic capacitance. The structure may further include one or more air gap structures formed upon the substrate and in between the graphene coated metal interconnect structures and capped with a dielectric layer.

公开(公告)号：US20230146034A1

公开(公告)日：2023-05-11

申请号：US17454570

申请日：2021-11-11

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Devika Sarkar Grant ,  SON NGUYEN

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12 ,  H01L45/1253 ,  H01L45/16

Abstract: An approach providing a semiconductor structure that provides a self-leveling, flowable, dielectric material for a gap fill material between vertical structures in many emerging non-volatile memory devices that are being formed with vertical structures for increasing memory device density. The semiconductor structure provides a flat dielectric surface between a plurality of contacts in a back end of the line metal layer in both the memory region and in the logic region of the semiconductor structure. The semiconductor structure includes a first portion of the plurality of contacts that each connect to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the contacts that each connect to a pillar-based memory device in the array of memory devices reside in a conventional interlayer dielectric material under the self-leveling dielectric material. The flowable, self-leveling material provides a flat dielectric surface during contact formation.

公开(公告)号：US20240332398A1

公开(公告)日：2024-10-03

申请号：US18191295

申请日：2023-03-28

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Roy R. Yu ,  SON NGUYEN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure with a nanosheet device region with GAA nanosheet FETs on a bottom dielectric isolation layer. The GAA nanosheet FETs connect by a frontside contact to the frontside back-end-of-line (BEOL) interconnect wiring and by a backside contact to the backside BEOL interconnect wiring. The semiconductor structure includes a finFET device region with one or more finFET devices on bottom interlayer dielectric material. The finFET devices with a thick gate oxide connect by a frontside contact to the frontside BEOL interconnect wiring. The semiconductor structure also includes a three-dimensional MIM capacitor region with one or more three-dimensional MIM capacitors. The three-dimensional MIM capacitors with a high capacitance have a fin-like backside metal plate covered by a high-k dielectric material or super capacitor materials that is under a frontside metal plate. The three-dimensional MIM capacitors connect to the frontside BEOL interconnect wiring and the backside BEOL interconnect wiring.

公开(公告)号：US20240312834A1

公开(公告)日：2024-09-19

申请号：US18185481

申请日：2023-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  SON NGUYEN ,  Matthew T. Shoudy ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76843 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A first BEOL layer, including a first and a second signal line, a conformal dielectric surrounding an upper portion of a vertical sidewall of each of the first signal line and the second signal line, an air gap between the first and the second signal line, a vertical side boundary of the air gap is a vertical side surface of the first signal line. Forming a first and a second metal line in a sacrificial material in a first BEOL layer, removing the sacrificial material, forming a conformal dielectric surrounding vertical side surfaces of the first and the second metal line, an air gap between the first and the second metal line exposes an upper horizontal surface of a dielectric layer below the first BEOL layer, growing a dielectric selectively from an upper portion of the conformal dielectric, the air gap remains between the first and the second metal line.

公开(公告)号：US20230238236A1

公开(公告)日：2023-07-27

申请号：US17586757

申请日：2022-01-27

Applicant: International Business Machines Corporation

Inventor： Cornelius Brown Peethala ,  Rudy J. Wojtecki ,  SON NGUYEN ,  Balasubramanian S. Pranatharthiharan

IPC: H01L21/02 ,  H01L23/522

CPC classification number: H01L21/02263 ,  H01L21/02118 ,  H01L23/5226

Abstract: An exemplary semiconductor structure includes a semiconductor substrate; a plurality of metal lines on top of the semiconductor substrate, each line having a line width 5 nanometers or less: a plurality of dielectric features adjacent to the metal lines; and a plurality of metal vias on top of the metal lines. Out of a random sample of 1000 vias at least 950 vias are fully-aligned to corresponding metal lines.

公开(公告)号：US20230197418A1

公开(公告)日：2023-06-22

申请号：US17556242

申请日：2021-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Rudy J. Wojtecki ,  Krystelle Lionti ,  Noel Arellano ,  SON NGUYEN

IPC: H01J37/32

CPC classification number: H01J37/32522 ,  H01J37/32009 ,  H01J2237/332

Abstract: A method of selectively forming a cover layer is provided. The method includes exposing a surface of a metal feature and a surface of a dielectric layer to a plasma treatment, and exposing the surface of a metal feature and a surface of a dielectric layer to an inhibitor species to form an inhibitor layer selectively on the surface of the metal feature. The method further includes polymerizing the inhibitor layer to form an inhibiting film, and forming the cover layer on the surface of the dielectric layer.

公开(公告)号：US20230178370A1

公开(公告)日：2023-06-08

申请号：US17542563

申请日：2021-12-06

Applicant: International Business Machines Corporation

Inventor： Rudy J. Wojtecki ,  Nicholas Anthony Lanzillo ,  PRASAD BHOSALE ,  SON NGUYEN

IPC: H01L21/027 ,  C23C16/04 ,  C23C16/56 ,  C23C16/02 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/0271 ,  C23C16/04 ,  C23C16/56 ,  C23C16/0227 ,  H01L21/02301 ,  H01L21/76829

Abstract: Embodiments of the invention provide self-assembled monolayers (SAM) formulations and cleaning to promote quick depositions. A hydrogen-based plasma clean is performed on a structure, the structure including a metal layer and a dielectric layer. A self-assembled monolayers (SAM) solution is dispensed on the structure, the SAM solution including SAMs and a solvent, the SAMs being configured to assemble on the metal layer. The structure is rinsed with a rinse solution including the solvent.

公开(公告)号：US20200083345A1

公开(公告)日：2020-03-12

申请号：US16127720

申请日：2018-09-11

Applicant: International Business Machines Corporation

Inventor： Donald Canaperi ,  Richard A. Conti ,  Thomas J. Haigh, JR. ,  ERIC MILLER ,  SON NGUYEN

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/417

Abstract: A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

公开(公告)号：US20240404949A1

公开(公告)日：2024-12-05

申请号：US18206060

申请日：2023-06-05

Applicant: International Business Machines Corporation

Inventor： SON NGUYEN ,  Ruilong Xie ,  Kisik Choi ,  Hosadurga Shobha

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Low-k, carbon-rich silicon carbonitride or silicon oxycarbonitride interlevel dielectric layers having good copper and oxidation barrier properties are employed to facilitate the manufacture and reliability of integrated circuits, including structures including back side power rails. Such interlevel dielectric layers enable copper to copper or copper to metal bonding without copper or metal diffusion into dielectric material, even with some misalignment.