公开(公告)号：US09147752B2

公开(公告)日：2015-09-29

申请号：US13972290

申请日：2013-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shu-Jen Han ,  Alberto Valdes Garcia

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/44 ,  H01L21/336 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66742 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78636 ,  H01L29/78684

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract translation: 具有降低的栅极电阻的器件包括具有第一导电部分和形成为与第一导电部分电接触并且横向延伸超过第一导电部分延伸的第二导电部分的栅极结构。 栅极结构嵌入电介质材料中，并且在第一导电部分上具有栅极电介质。 沟道层设置在第一导电部分上。 源极和漏极形成在沟道层的沟道区的相对端部上。 还提供了形成栅极电阻降低的器件的方法。

公开(公告)号：US09103776B2

公开(公告)日：2015-08-11

申请号：US13970637

申请日：2013-08-20

Applicant: International Business Machines Corporation

Inventor： Ali Afzali-Ardakani ,  Shu-Jen Han

IPC: G01N33/543 ,  G01N27/414 ,  H01L51/00 ,  B82Y10/00 ,  B82Y15/00 ,  G01N33/551 ,  H01L51/05 ,  B82Y40/00

CPC classification number: G01N27/4146 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y40/00 ,  G01N33/5438 ,  G01N33/551 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0067 ,  H01L51/0072 ,  H01L51/0558

Abstract: Sensors, processes for manufacturing the sensors, and processes of detecting a target molecule with the sensor generally includes a substrate including a channel and first and second electrodes electrically connected to the channel, wherein the channel includes a monolayer of surface functionalized graphene or surface functionalized carbon nanotubes, wherein the surface functionalized graphene or surface functionalized carbon nanotubes include an imidazolidone compound.

公开(公告)号：US09087811B2

公开(公告)日：2015-07-21

申请号：US13969013

申请日：2013-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/16 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管，嵌入基板中的栅极结构; 嵌入在栅极结构周围的衬底中的自对准源极和漏极接触; 以及栅极结构和自对准源极和漏极触点之间的沟道层。 源极和漏极触点在沟道层上方延伸。

公开(公告)号：US20150194619A1

公开(公告)日：2015-07-09

申请号：US14150275

申请日：2014-01-08

Applicant: International Business Machines Corporation

Inventor： Aaron D. Franklin ,  Shu-Jen Han ,  Satyavolu S. Papa Rao ,  Joshua T. Smith

IPC: H01L51/05 ,  H01L51/00

CPC classification number: H01L51/0554 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  H01L51/0558

Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate comprising filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.

Abstract translation: 本发明的实施例包括制造方法和半导体结构。 制造方法包括在衬底上沉积第一介电材料，以及形成底栅，包括用第一导电材料填充第一介电层中的第一开口。 接下来，沉积第二介电材料，并在第二电介质材料中形成沟槽，直到第一导电材料。 接下来，在沟槽的侧壁上沉积第二导电材料，形成第一导电材料和第二导电材料之间的电连接，在沟槽中沉积第三电介质材料，以及除去不在沟槽中的多余材料。 接下来，沉积栅极电介质层，并在栅极电介质层上形成碳纳米管的沟道层。 最后，在形成源极和漏极端子的沟道层上沉积第三导电材料。

公开(公告)号：US20150191842A1

公开(公告)日：2015-07-09

申请号：US14666876

申请日：2015-03-24

Applicant: International Business Machines Corporation

Inventor： Lian Guo ,  Shu-Jen Han ,  Xuesong Li

IPC: C25D17/00 ,  C25F7/00

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/184 ,  C01B32/186 ,  C01B32/20 ,  C01B32/21 ,  C25D17/007 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

公开(公告)号：US20150187764A1

公开(公告)日：2015-07-02

申请号：US14643224

申请日：2015-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions.

Abstract translation: 堆叠晶体管器件包括具有形成在衬底上的下沟道层的下晶体管，以及直接形成在下沟道层上的下源极和漏区。 下部源极和漏极区域与形成在衬底中的各个导电源极和漏极延伸部电接触。 上部晶体管具有与相应的下部源极和漏极区垂直对准的上部源极和漏极区域。 上部源极和漏极区域通过绝缘体与相应的下部源极和漏极区域分离。 上部晶体管还包括形成在上部源极和漏极区域上的上部沟道层。

公开(公告)号：US09059272B2

公开(公告)日：2015-06-16

申请号：US13950841

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66628

Abstract: A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

Abstract translation: 一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。 形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源/漏区上生长金属接触。 还公开了晶体管和计算机程序产品。

公开(公告)号：US09059271B2

公开(公告)日：2015-06-16

申请号：US13950777

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66628

Abstract: A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

公开(公告)号：US09048216B2

公开(公告)日：2015-06-02

申请号：US13864760

申请日：2013-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/16 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹部中形成源极和漏极接触，其中源极和漏极接触在沟道层上方延伸。

公开(公告)号：US08994080B2

公开(公告)日：2015-03-31

申请号：US13968101

申请日：2013-08-15

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.

Abstract translation: 堆叠晶体管器件包括形成在衬底上的下沟道层; 一对垂直对齐的源极区，形成在所述下部沟道层上，其中所述一对源极区被绝缘体隔开; 形成在下通道层上的一对垂直排列的漏极区，其中一对漏区由绝缘体分隔开; 形成在下栅极电介质层上的一对垂直排列的栅极区; 以及形成在源极区域，漏极区域和栅极区域上的上部沟道层。