公开(公告)号：US20150318211A1

公开(公告)日：2015-11-05

申请号：US14610653

申请日：2015-01-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： DECHAO GUO ,  SHOGO MOCHIZUKI ,  ANDREAS SCHOLZE ,  CHUN-CHEN YEH

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

Abstract translation: 一种半导体器件，其包括鳍结构的沟道区域上的栅极结构，以及鳍状结构的源极区域和漏极区域上的外延源区域和外延漏极区域中的至少一个。 外延源区域部分和外延漏极区域部分中的至少一个包括与鳍状结构相邻的第一浓度掺杂部分和第一浓度掺杂部分上的第二浓度掺杂部分。 第二浓度部分具有比第一浓度掺杂部分更大的掺杂剂浓度。 扩展掺杂剂区域延伸到鳍结构的沟道部分，其具有每十年或更长时间为7nm的n型或p型掺杂剂的突变掺杂剂浓度梯度。

公开(公告)号：US20150187764A1

公开(公告)日：2015-07-02

申请号：US14643224

申请日：2015-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions.

Abstract translation: 堆叠晶体管器件包括具有形成在衬底上的下沟道层的下晶体管，以及直接形成在下沟道层上的下源极和漏区。 下部源极和漏极区域与形成在衬底中的各个导电源极和漏极延伸部电接触。 上部晶体管具有与相应的下部源极和漏极区垂直对准的上部源极和漏极区域。 上部源极和漏极区域通过绝缘体与相应的下部源极和漏极区域分离。 上部晶体管还包括形成在上部源极和漏极区域上的上部沟道层。

公开(公告)号：US20230170352A1

公开(公告)日：2023-06-01

申请号：US17538559

申请日：2021-11-30

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  JUNLI WANG ,  DECHAO GUO

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02609 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66742

Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets (NS) and a method of forming such a structure. The structure is a three dimensional (3D) integration by vertically stacking nFETs and pFETs for area scaling. In an embodiment, vertically-stacked NS FET structures include a first nanosheet transistor located above a second nanosheet transistor; the first nanosheet transistor including a first NS channel material, wherein the first NS channel material includes a first crystalline orientation; the second nanosheet transistor including a second NS channel material, wherein the second NS channel material comprises a second crystalline orientation, the first crystalline orientation is different from the second crystalline orientation. In an embodiment, each of the respective formed vertically-stacked NS FET structures include respective suspended stack of nanosheet channels that are self-aligned with each other.

公开(公告)号：US20170294510A1

公开(公告)日：2017-10-12

申请号：US15634411

申请日：2017-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RENESAS ELECTRONICS CORPORATION

Inventor： DECHAO GUO ,  SHOGO MOCHIZUKI ,  ANDREAS SCHOLZE ,  CHUN-CHEN YEH

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/324 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

公开(公告)号：US20160276463A1

公开(公告)日：2016-09-22

申请号：US15170273

申请日：2016-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RENESAS ELECTRONICS CORPORATION

Inventor： DECHAO GUO ,  SHOGO MOCHIZUKI ,  ANDREAS SCHOLZE ,  CHUN-CHEN YEH

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

公开(公告)号：US20140312412A1

公开(公告)日：2014-10-23

申请号：US13864760

申请日：2013-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  SHU-JEN HAN ,  YU LU ,  KEITH KWONG HON WONG

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹部中形成源极和漏极接触，其中源极和漏极接触在沟道层上方延伸。

公开(公告)号：US20130244386A1

公开(公告)日：2013-09-19

申请号：US13863017

申请日：2013-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  SHU-JEN HAN ,  KEITH KWONG HON WONG ,  JUN YUAN

IPC: H01L29/66

CPC classification number: H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract translation: 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅电极，并且在掩埋栅电极之上构图包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20160284701A1

公开(公告)日：2016-09-29

申请号：US15170299

申请日：2016-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RENESAS ELECTRONICS CORPORATION

Inventor： DECHAO GUO ,  SHOGO MOCHIZUKI ,  ANDREAS SCHOLZE ,  CHUN-CHEN YEH

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

Abstract translation: 一种半导体器件，其包括鳍结构的沟道区域上的栅极结构，以及鳍状结构的源极区域和漏极区域上的外延源区域和外延漏极区域中的至少一个。 外延源区部分和外延漏区部分中的至少一个包括与鳍结构相邻的第一浓度掺杂部分和第一浓度掺杂部分上的第二浓度掺杂部分。 第二浓度部分具有比第一浓度掺杂部分更大的掺杂剂浓度。 扩展掺杂剂区域延伸到鳍结构的沟道部分，其具有每十年或更长时间为7nm的n型或p型掺杂剂的突变掺杂剂浓度梯度。

公开(公告)号：US20150228753A1

公开(公告)日：2015-08-13

申请号：US14698206

申请日：2015-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DECHAO GUO ,  SHU-JEN HAN ,  YU LU ,  KEITH KWONG HON WONG

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/306 ,  H01L21/04 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹槽中形成源极和漏极接触。 源极和漏极触点在沟道层上方延伸。