公开(公告)号：US07608498B2

公开(公告)日：2009-10-27

申请号：US12003802

申请日：2008-01-02

申请人： Takuya Kobayashi ,  Katsuyuki Sekine ,  Tomonori Aoyama ,  Hiroshi Tomita

发明人： Takuya Kobayashi ,  Katsuyuki Sekine ,  Tomonori Aoyama ,  Hiroshi Tomita

IPC分类号： H01L21/336

CPC分类号： H01L21/02148 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/31645 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/6656

摘要： A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上的层间电介质膜中形成沟槽，沟槽到达半导体衬底并具有由氮化硅膜制成的侧壁; 在200摄氏度至260摄氏度的温度范围内沉积由HfSiO膜制成的栅极绝缘膜，使得HfSiO膜沉积在暴露于沟槽底表面的半导体衬底上，而不沉积HfSiO 膜上的氮化硅膜; 并用金属制成的栅电极填充沟槽。

公开(公告)号：US20080128758A1

公开(公告)日：2008-06-05

申请号：US11907349

申请日：2007-10-11

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Katsuyuki Sekine ,  Yuji Saito

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Katsuyuki Sekine ,  Yuji Saito

IPC分类号： H01L29/04

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28238 ,  H01L27/11521 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/40111 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/7883

摘要： A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.

摘要翻译： 半导体器件包括在（111）表面附近具有晶体表面的Si晶体和形成在所述晶体表面上的绝缘膜，所述绝缘膜的至少一部分包括含有Kr或Si氮化物的Si氧化物膜 含Ar或Kr的薄膜。

公开(公告)号：US07375403B2

公开(公告)日：2008-05-20

申请号：US10738049

申请日：2003-12-18

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物构成的栅极绝缘膜， 或四价金属氧化物和SiON的混合物，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且栅电极 由功能为4eV至5.5eV的金属制成。

公开(公告)号：US20080054378A1

公开(公告)日：2008-03-06

申请号：US11889278

申请日：2007-08-10

申请人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

发明人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

IPC分类号： H01L29/76

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/78

摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

摘要翻译： 一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极 高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为 主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜 含有SiO 2作为主要成分的Hf，Zr和N.

公开(公告)号：US07160818B2

公开(公告)日：2007-01-09

申请号：US11020271

申请日：2004-12-27

申请人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

发明人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： An aspect of the present invention includes; a silicon oxynitride film having an oxynitride layer which is formed on at least the surface of a silicon substrate and in which nitrogen atoms are in a three-coordinate bond state, and a silicon oxide layer which is formed between said oxynitride layer and said silicon substrate.

摘要翻译： 本发明的一个方面包括： 一种氧氮化硅膜，其形成在至少在硅衬底的表面上并且其中氮原子处于三坐标结合状态的氧氮化物层和形成在所述氧氮化物层和所述硅衬底之间的氧化硅层 。

公开(公告)号：US20060273413A1

公开(公告)日：2006-12-07

申请号：US11185678

申请日：2005-07-21

申请人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

发明人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

IPC分类号： H01L29/94

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at both sides of the first gate electrode in the first device region; a second gate insulating film of a high-k material which is different from the high-k material of the first gate insulating film, the second gate insulating film being formed in the second device region; a second gate electrode formed on the second gate insulating film; and second source and drain regions formed at both sides of the second gate electrode in the second device region.

摘要翻译： 提供：包括由器件隔离区域隔离的第一和第二器件区域的半导体衬底; 形成在所述第一器件区域中的高k材料的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的第一栅电极; 形成在第一器件区域中的第一栅电极的两侧的第一源极和漏极区; 与所述第一栅极绝缘膜的高k材料不同的高k材料的第二栅极绝缘膜，所述第二栅极绝缘膜形成在所述第二器件区域中; 形成在所述第二栅极绝缘膜上的第二栅电极; 以及形成在第二器件区域中的第二栅电极的两侧的第二源极和漏极区。

公开(公告)号：US07141466B2

公开(公告)日：2006-11-28

申请号：US10962673

申请日：2004-10-13

申请人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

发明人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/518 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/78

摘要： According to the present invention, there is provided a semiconductor device comprising:an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer;a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film;a gate electrode formed on said gate insulating film; andsource and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：界面绝缘膜，其选择性地形成在半导体衬底的预定区域上，并且具有基本上一个原子层的膜厚度; 形成在所述界面绝缘膜上并具有高于所述界面绝缘膜的介电常数的介电常数的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及源极和漏极区，形成在位于所述栅电极下方的沟道区的两侧的所述半导体衬底的表面区域中。

公开(公告)号：US20060093731A1

公开(公告)日：2006-05-04

申请号：US11260253

申请日：2005-10-28

申请人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

IPC分类号： C23C16/52 ,  H05H1/24 ,  B05C11/00 ,  C23C16/00

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069 ,  H01L22/14

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

公开(公告)号：US20050236678A1

公开(公告)日：2005-10-27

申请号：US10962673

申请日：2004-10-13

申请人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

发明人： Motoyuki Sato ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Akio Kaneko

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L29/518 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/78

摘要： According to the present invention, there is provided a semiconductor device comprising: an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer; a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film; a gate electrode formed on said gate insulating film; and source and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：界面绝缘膜，其选择性地形成在半导体衬底的预定区域上，并且具有基本上一个原子层的膜厚度; 形成在所述界面绝缘膜上并具有高于所述界面绝缘膜的介电常数的介电常数的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及源极和漏极区，形成在位于所述栅电极下方的沟道区的两侧的所述半导体衬底的表面区域中。

公开(公告)号：US5123860A

公开(公告)日：1992-06-23

申请号：US770551

申请日：1991-10-03

申请人： Takeo Kamei ,  Katsuyuki Sekine

发明人： Takeo Kamei ,  Katsuyuki Sekine

IPC分类号： H01R13/648 ,  H01R9/05 ,  H01R13/58

CPC分类号： H01R9/0521

摘要： A grounding connector for a shielded cable comprising a backshell, a cap nut, and a ring therebetween, wherein the ring is of a novel design having a single slit and at least three protrusions extending axially toward the cap nut, whereby previously used tube, stepped ring, and spring washers are all eliminated. The invention is thus substantially simplified from the prior art, has enhanced EMI prevention properties, greatly reduced costs, and greatly increased reliability, and improved performance.

摘要翻译： 一种用于屏蔽电缆的接地连接器，包括后壳，盖帽螺母和其间的环，其中环具有新颖的设计，其具有单个狭缝和至少三个沿盖帽螺母轴向延伸的突起，由此预先使用的管，阶梯 环和弹簧垫圈均已消除。 因此，本发明从现有技术大大简化，具有增强的EMI防止性能，大大降低成本，并且大大提高可靠性和改进的性能。