公开(公告)号：US11782721B2

公开(公告)日：2023-10-10

申请号：US17680538

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Aaron P. Boehm ,  Fa-Long Luo

IPC: G06F9/38 ,  G06F9/30 ,  G11C7/10 ,  G11C7/08

CPC classification number: G06F9/3855 ,  G06F9/3001 ,  G06F9/30018 ,  G11C7/08 ,  G11C7/1006 ,  G06F9/30032

Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

公开(公告)号：US11775385B2

公开(公告)日：2023-10-03

申请号：US17580284

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/10 ,  H03M13/29 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/22

CPC classification number: G06F11/1068 ,  H03M13/2906 ,  G11C11/221 ,  G11C11/4087 ,  G11C11/4091

Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device receives a command (e.g., a write command or a read command) from a host device over a first set of pins and performs data transfer over a second set of pins with the host device according to the command. The memory device exchanges a first parity bit associated with the command with the host device, and generates a second parity bit based on the command. A parity result bit is subsequently generated based, at least in part, on the first parity bit and the second parity bit.

公开(公告)号：US11751031B2

公开(公告)日：2023-09-05

申请号：US17708781

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Glen E. Hush ,  Aaron P. Boehm

IPC: G06F3/06 ,  H04W4/70 ,  H04W72/04 ,  H04W72/12 ,  H04W74/02 ,  H04W74/04 ,  H04W74/08 ,  H04W76/14 ,  H04W88/06 ,  H04W92/18 ,  H04W72/0453 ,  H04W72/23

CPC classification number: H04W4/70 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  H04W72/0453 ,  H04W72/12 ,  H04W72/1215 ,  H04W72/23 ,  H04W74/02 ,  H04W74/04 ,  H04W74/08 ,  H04W76/14 ,  H04W88/06 ,  H04W92/18

Abstract: Methods, apparatuses, and systems related to wireless main memory for computing are described. A device may include a processor that is wirelessly coupled to a memory array, which may be in a physically separate device. The processor may execute instructions stored in and wirelessly communicated from the memory array. The processor may read data from or write data to the memory array via a wireless communication link (e.g., using resources of an ultra high frequency, super high frequency, and/or extremely high frequency band). Several devices may have a small amount of local memory (or no local memory) and may share, via a wireless communication link, a main memory array. Memory devices may include memory resources and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).

公开(公告)号：US20230205874A1

公开(公告)日：2023-06-29

申请号：US17653265

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: Methods, systems, and devices for voltage input and clock speed change determination to detect an attack are described. In some systems, a memory device may receive first signaling indicative of a first value for an input (e.g., voltage input, clock speed) to the memory device. The memory device may further receive second signaling indicative of a second (e.g., time-delayed) value for the input to the memory device. The memory device may detect a change to the input based on the first signaling and the second signaling. For example, the memory device may compare the first signaling to the second signaling, may compare a difference between the first signaling and the second signaling to a threshold, or both. If the input changes (e.g., by a threshold amount), the memory device may disable one or more features to protect against an attack on the memory device.

公开(公告)号：US20230205615A1

公开(公告)日：2023-06-29

申请号：US18068152

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Aaron P. Boehm

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/073 ,  G06F11/079

Abstract: Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a “1”) indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a “0”), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.

公开(公告)号：US20230197182A1

公开(公告)日：2023-06-22

申请号：US18108302

申请日：2023-02-10

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G11C29/12 ,  G06F12/02

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G06F12/0238 ,  G06F2212/7211 ,  G11C2207/2254 ,  G06F2212/7201

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US11675662B2

公开(公告)日：2023-06-13

申请号：US17348211

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

CPC classification number: G06F11/1072 ,  G06F11/1012 ,  G06F11/1052 ,  G11C7/1018

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US11650952B2

公开(公告)日：2023-05-16

申请号：US17494980

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: G06F15/173 ,  H04L67/1097 ,  H04W88/06 ,  H04W4/44

CPC classification number: G06F15/17331 ,  H04L67/1097 ,  H04W4/44 ,  H04W88/06

Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources via a base station are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first memory resource, a first processor coupled to the first memory resource, and a wireless base station coupled to the first processor. The first memory resource, the first processor, and the base station are configured to enable formation of a memory pool between the first memory resource and a second memory resource at a vehicle responsive to a request to access the second memory resource from the first processor transmitted via the base station.

公开(公告)号：US20230062939A1

公开(公告)日：2023-03-02

申请号：US17816320

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  G06F11/07 ,  H03M13/00

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

公开(公告)号：US11586383B2

公开(公告)日：2023-02-21

申请号：US16579153

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06 ,  G06F21/79 ,  G06F12/14

Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).