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    Constructions Comprising Stacked Memory Arrays
    122.
    发明申请
    Constructions Comprising Stacked Memory Arrays 有权
    包含堆叠内存数组的构造

    公开(公告)号：US20160276022A1

    公开(公告)日：2016-09-22

    申请号：US14662920

    申请日：2015-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: G11C13/00

    CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

    Abstract translation: 一些实施例包括具有第一存储器阵列甲板和在第一存储器阵列甲板上的第二存储器阵列甲板的结构。 第二存储器阵列板与第一存储器阵列板的不同之处在于一个或多个工作特性，间距和/或一个或多个结构参数; 其结构参数包括不同材料和/或不同厚度的材料。 一些实施例包括具有沿着第一方向延伸的第一系列和第三系列存取/检测线的结构，以及在第一和第三系列之间的第二系列的存取/感测线，并且沿第二方向延伸，该第二方向穿过第一方向 。 第一存储单元位于第一和第二系列存取/检测线之间，并且布置在第一存储器阵列板中。 第二存储器单元位于第二和第三系列存取/检测线之间，并且布置在第二存储器阵列板中。

    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS
    126.
    发明申请
    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS 有权
    形成电阻随机访问记忆与保险丝阵列

    公开(公告)号：US20150280123A1

    公开(公告)日：2015-10-01

    申请号：US14738453

    申请日：2015-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto Maria Meotto ,  Giorgio Servalli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

    Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。

    Forming resistive random access memories together with fuse arrays
    127.
    发明授权
    Forming resistive random access memories together with fuse arrays 有权
    形成电阻随机存取存储器和熔丝阵列

    公开(公告)号：US09136471B2

    公开(公告)日：2015-09-15

    申请号：US14066308

    申请日：2013-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto M. Meotto ,  Giorgio Servalli

    IPC: H01L21/82 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

    Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。

    MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS
    128.
    发明申请
    MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS 有权
    具有多种电阻变化材料的记忆体

    公开(公告)号：US20150138880A1

    公开(公告)日：2015-05-21

    申请号：US14596293

    申请日：2015-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/16

    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

    Abstract translation: 具有多个电阻变化材料的电阻变量存储单元及其操作和形成方法在此描述。 作为示例，电阻可变存储单元可以包括位于插塞材料和电极材料之间的多个电阻变化材料。 电阻可变存储单元还包括接触插塞材料和多个电阻可变材料中的每一个的第一导电材料和接触电极材料和多个电阻可变材料中的每一个的第二导电材料。

    Memory Constructions
    129.
    发明申请
    Memory Constructions 有权
    记忆建筑

    公开(公告)号：US20150014623A1

    公开(公告)日：2015-01-15

    申请号：US14503081

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。

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