公开(公告)号：US20210342263A1

公开(公告)日：2021-11-04

申请号：US17378212

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

公开(公告)号：US11112982B2

公开(公告)日：2021-09-07

申请号：US16552243

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David A. Palmer

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10

Abstract: A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.

公开(公告)号：US11074989B2

公开(公告)日：2021-07-27

申请号：US16079737

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  John Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US20210064256A1

公开(公告)日：2021-03-04

申请号：US16552243

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David A. Palmer

IPC: G06F3/06 ,  G06F11/10

Abstract: A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies he threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executs the operation at the increased drive strength value of the storage device.

公开(公告)号：US20210012851A1

公开(公告)日：2021-01-14

申请号：US16079737

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulache Tanpairoj ,  John Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20 ,  G11C29/14 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US10824527B2

公开(公告)日：2020-11-03

申请号：US16504067

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G11C16/34 ,  G06F11/20 ,  G11C29/00 ,  G06F11/10 ,  G11C16/04

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US10394479B2

公开(公告)日：2019-08-27

申请号：US15749402

申请日：2015-08-20

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He

IPC: G06F3/06 ,  G11C29/52 ,  G06F9/4401 ,  G06F11/10

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information on stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US10223198B2

公开(公告)日：2019-03-05

申请号：US15046666

申请日：2016-02-18

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Sampath K. Ratnam

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  H03M13/15 ,  H03M13/13 ,  H03M13/00 ,  H04L1/00 ,  H03M13/29 ,  H03M13/35 ,  G11C29/04

Abstract: The present disclosure includes apparatuses and methods for error rate reduction. One example method comprises adding an amount of error rate reduction (ERR) data to an amount of received user data, and writing the amount of user data along with the amount of ERR data to a memory.