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公开(公告)号：US10354729B1
公开(公告)日：2019-07-16
申请号：US15857188
申请日：2017-12-28
Applicant: Micron Technology, Inc.
Inventor： Hongmei Wang , Luca Crespi , Debayan Mahalanabis , Fabio Pellizzer
IPC: G11C13/00
Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.
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公开(公告)号：US20190206506A1
公开(公告)日：2019-07-04
申请号：US16284491
申请日：2019-02-25
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
CPC classification number: G11C29/00 , G11C13/00 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C29/52 , G11C2013/0052 , G11C2213/71 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US20190180817A1
公开(公告)日：2019-06-13
申请号：US16279585
申请日：2019-02-19
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer , Ferdinando Bedeschi
IPC: G11C13/00
Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.
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公开(公告)号：US10283198B2
公开(公告)日：2019-05-07
申请号：US15588301
申请日：2017-05-05
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.
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公开(公告)号：US10276235B2
公开(公告)日：2019-04-30
申请号：US15980480
申请日：2018-05-15
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Davide Fugazza , Johannes A. Kalb
Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.
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Patent Agency Ranking
公开(公告)号：US10269442B1
公开(公告)日：2019-04-23
申请号：US15857125
申请日：2017-12-28
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US20190067571A1
公开(公告)日：2019-02-28
申请号：US15687038
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer
CPC classification number: H01L45/1246 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1253 , H01L45/141 , H01L45/1683
Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.
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公开(公告)号：US10153040B2
公开(公告)日：2018-12-11
申请号：US15828402
申请日：2017-11-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Fabio Pellizzer , Hari Giduturi , Mingdong Cui
Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.
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公开(公告)号：US20180315474A1
公开(公告)日：2018-11-01
申请号：US15582321
申请日：2017-04-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
CPC classification number: G11C13/0004 , G11C11/005 , G11C11/5678 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/73 , G11C2213/77
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US10102905B2
公开(公告)日：2018-10-16
申请号：US15617381
申请日：2017-06-08
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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