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    MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES
    121.
    发明申请
    MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES 有权

    公开(公告)号：US20210350838A1

    公开(公告)日：2021-11-11

    申请号：US17328211

    申请日：2021-05-24

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

    IPC: G11C7/10 ,  G11C5/04

    Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

    Memory Systems, Modules, and Methods for Improved Capacity
    122.
    发明申请
    Memory Systems, Modules, and Methods for Improved Capacity 有权

    公开(公告)号：US20210294531A1

    公开(公告)日：2021-09-23

    申请号：US17235629

    申请日：2021-04-20

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Scott C. Best

    IPC: G06F3/06 ,  G11C5/04 ,  G06F13/16

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

    Memory module and system supporting parallel and serial access modes
    123.
    发明授权
    Memory module and system supporting parallel and serial access modes 有权

    公开(公告)号：US11049532B2

    公开(公告)日：2021-06-29

    申请号：US15721755

    申请日：2017-09-30

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

    IPC: G11C7/10 ,  G11C5/04

    Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

    MULTI-DIE MEMORY DEVICE
    124.
    发明申请
    MULTI-DIE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200321047A1

    公开(公告)日：2020-10-08

    申请号：US16823122

    申请日：2020-03-18

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    Strobe-offset control circuit
    125.
    发明授权
    Strobe-offset control circuit 有权

    公开(公告)号：US10741237B2

    公开(公告)日：2020-08-11

    申请号：US16106355

    申请日：2018-08-21

    Applicant: Rambus Inc.

    Inventor： Scott C. Best

    IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/04 ,  G06F13/16

    Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

    Multi-die memory device
    126.
    发明授权
    Multi-die memory device 有权

    公开(公告)号：US10607691B2

    公开(公告)日：2020-03-31

    申请号：US16211966

    申请日：2018-12-06

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406 ,  H01L23/00

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    Stacked semiconductor device assembly in computer system
    128.
    发明授权
    Stacked semiconductor device assembly in computer system 有权

    公开(公告)号：US10445269B2

    公开(公告)日：2019-10-15

    申请号：US16175645

    申请日：2018-10-30

    Applicant: Rambus Inc.

    Inventor： Scott C. Best

    IPC: G06F13/36 ,  G06F13/362 ,  H01L23/48 ,  H01L23/60 ,  H01L25/065 ,  G11C11/408 ,  G11C11/409 ,  H01L23/50 ,  H01L23/00 ,  G06F13/40 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L27/02

    Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS
    129.
    发明申请
    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS 审中-公开

    公开(公告)号：US20190114271A1

    公开(公告)日：2019-04-18

    申请号：US16164242

    申请日：2018-10-18

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ian Shaeffer

    IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/409 ,  G11C11/4076 ,  G06F3/06

    Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

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