公开(公告)号：US20080093654A1

公开(公告)日：2008-04-24

申请号：US11962615

申请日：2007-12-21

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US20070276189A1

公开(公告)日：2007-11-29

申请号：US10561649

申请日：2004-06-24

申请人： Eric Abel ,  James Hewit ,  Alan Slade ,  Zhigang Wang

发明人： Eric Abel ,  James Hewit ,  Alan Slade ,  Zhigang Wang

IPC分类号： A61B1/06 ,  A61B17/02

CPC分类号： A61B1/32 ,  A61B1/31 ,  A61M29/00

摘要： There is disclosed medical apparatus of the type for use in surgery such as transanal endoscopic microsurgery, as well as methods of providing access to, inspecting and enabling surgery within a body passage. In one embodiment of the invention, medical apparatus in the form of a rectal expander (10) is disclosed, the expander (10) being adapted for location at least partly within a body passage such as the rectum (12) of a patient (14), the expander (10) having a leading end (18) and an access area in the form of an opening (20) for access from the expander (10) into the rectum (12), at least part of the opening (20) being spaced from the leading end (18), and the expander (10) being controllably movable between collapse and expansion positions, for expanding the rectum (12).

摘要翻译： 公开了用于外科手术的类型的医疗装置，例如经肛门内窥镜显微外科手术，以及提供身体通道内的进入，检查和使手术的方法。 在本发明的一个实施例中，公开了直肠扩张器（10）形式的医疗装置，所述扩张器（10）适于至少部分位于身体通道内，例如患者（14）的直肠（12） ），所述膨胀器（10）具有前端（18）和开口（20）形式的进入区域，用于从所述膨胀器（10）进入直肠（12），所述开口（20）的至少一部分 ）与所述前端（18）间隔开，并且所述膨胀器（10）可控制地在塌缩和膨胀位置之间移动，用于扩张直肠（12）。

公开(公告)号：US07272060B1

公开(公告)日：2007-09-18

申请号：US11001940

申请日：2004-12-01

申请人： Qiang Lu ,  Richard Fastow ,  Zhigang Wang

发明人： Qiang Lu ,  Richard Fastow ,  Zhigang Wang

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/12

摘要： A method, system, and circuit for performing a memory related operation are disclosed. An operating voltage is applied to a bitline and a neighboring bitline is precharged. The precharge voltage has a magnitude less than the operating voltage. Both voltages ramp up at like or different rates. The precharge voltage can reach its effective magnitude prior to or with the operating voltage reaching its effective value.

摘要翻译： 公开了一种用于执行存储器相关操作的方法，系统和电路。 工作电压施加到位线，并且相邻位线被预充电。 预充电电压的幅度小于工作电压。 两个电压都以相同或不同的速率上升。 预充电电压可以在工作电压达到其有效值之前或达到其有效幅度。

公开(公告)号：US07210082B1

公开(公告)日：2007-04-24

申请号：US11140579

申请日：2005-05-31

申请人： Khader S. Abdel-Hafez ,  Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Wang ,  Zhigang Jiang

发明人： Khader S. Abdel-Hafez ,  Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Wang ,  Zhigang Jiang

IPC分类号： G01R31/28 ,  G11B5/00 ,  G06F11/00

CPC分类号： G06F11/261 ,  G01R31/318307 ,  G01R31/318547

摘要： A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code 701 based on the Input Constraints 702 and a Foundry Library 703, into a Sequential Circuit Model 705. The Sequential Circuit Model 705 is then transformed 706 into an equivalent Combinational Circuit Model 707 for performing Forward and/or Backward Clock Analysis 708 to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model 707. The analysis results are used for Uncontrollable/Unobservable Labeling 709 of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation 710 are performed according to the Uncontrollable/Unobservable Labeling 709 to generate the HDL Test Benches and ATE Test Programs 711.

摘要翻译： 一种在所选择的扫描测试模式或选定的自测模式中，基于所选择的捕获操作中所选择的时钟顺序，在基于扫描的集成电路中执行ATPG（自动测试模式生成）和故障模拟的方法。 该方法包括将基于输入约束702和晶圆库703的RTL（寄存器传送级）或门级HDL（硬件描述语言）代码701编译成顺序电路模型705。 然后将顺序电路模型705转换为等效的组合电路模型707，以执行前向和/或后向时钟分析708，以确定组合电路模型707中所有组合逻辑门的所有输入和输出的驱动和观察时钟。 分析结果用于组合逻辑门的所选输入和输出的不可控/不可观察标签709。 最后，ATPG和/或故障模拟710根据不可控/不可观察的标签709执行，以产生HDL测试台和ATE测试程序711。

公开(公告)号：US20070045539A1

公开(公告)日：2007-03-01

申请号：US11509059

申请日：2006-08-24

申请人： Ritsuo Fukaya ,  Hidetoshi Sato ,  Zhigang Wang ,  Noriaki Arai ,  Makoto Ezumi

发明人： Ritsuo Fukaya ,  Hidetoshi Sato ,  Zhigang Wang ,  Noriaki Arai ,  Makoto Ezumi

IPC分类号： G21K7/00

CPC分类号： H01J37/28 ,  H01J2237/22

摘要： A scanning electron microscope is disclosed. The primary electron beam is radiated on a reticle (specimen), and an observation image of the reticle is obtained using the electrons secondarily released. The microscope comprises a lamp for radiating the vacuum ultraviolet light having the wavelength of not more than 172 nm on the reticle in the atmosphere, a radiation chamber for hermetically sealing the reticle so that the vacuum ultraviolet light can be radiated on the reticle, and a specimen holder for holding the reticle in the radiation chamber and capable of adjusting the distance between the lamp and the reticle.

摘要翻译： 公开了一种扫描电子显微镜。 将一次电子束照射在标线（样品）上，并使用二次释放的电子获得掩模版的观察图像。 显微镜包括用于在大气中的掩模版上照射波长不大于172nm的真空紫外光的灯，用于气密地密封掩模版的辐射室，以便可以将真空紫外光照射在掩模版上，并且 用于将掩模版保持在辐射室中并且能够调节灯和掩模版之间的距离的样本保持器。

公开(公告)号：US07151028B1

公开(公告)日：2006-12-19

申请号：US10981174

申请日：2004-11-04

申请人： Shenqing Fang ,  Rinji Sugino ,  Kuo-Tung Chang ,  Zhigang Wang ,  Kazuhiro Mizutani ,  Pavel Fastenko

发明人： Shenqing Fang ,  Rinji Sugino ,  Kuo-Tung Chang ,  Zhigang Wang ,  Kazuhiro Mizutani ,  Pavel Fastenko

IPC分类号： H01L21/26

CPC分类号： H01L29/66636 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.

摘要翻译： 根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成邻近层叠栅极结构的源极侧壁的第一间隔物的步骤，其中堆叠的栅极结构位于 基质。 该方法还包括在衬底的源区中形成与第一间隔物相邻的高能注入掺杂区。 该方法还包括在源极区域中形成凹部，其中凹部的侧壁位于与浮动栅极存储单元的源极相邻处，并且其中形成凹槽包括移除第一间隔物。 该方法还包括形成邻近层叠栅极结构的源极侧壁的第二间隔物，其中第二间隔物延伸到凹部的底部，并且其中第二间隔物包括等离子体生长的氧化物。

公开(公告)号：US20060242502A1

公开(公告)日：2006-10-26

申请号：US11348519

申请日：2006-02-07

申请人： Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Jiang ,  Zhigang Wang ,  Shianling Wu

发明人： Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Jiang ,  Zhigang Wang ,  Shianling Wu

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/318533 ,  G01R31/318591 ,  G01R31/31926

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.

摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。 所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。 在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。 消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

公开(公告)号：US06898124B1

公开(公告)日：2005-05-24

申请号：US10678446

申请日：2003-10-03

申请人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

发明人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

IPC分类号： G11C11/56 ,  G11C16/06 ,  G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.

摘要翻译： 示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。 感测电路还包括连接到第一晶体管的去耦电路。 解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。 去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。 利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

公开(公告)号：US06884638B1

公开(公告)日：2005-04-26

申请号：US10225052

申请日：2002-08-20

申请人： Tien-Chun Yang ,  Nian Yang ,  Zhigang Wang

发明人： Tien-Chun Yang ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L21/336 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L29/66825 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a flash memory device by determining the active region width (10) of a semiconductor device (27) using a measuring technique for the source drain overdrive current elements (31, 32, 33) having different active region widths and using that difference to establish the difference between the active region width of the devices (31, 32, 33) and the drawn width and using the difference to establish the actual width (10) from drawn width in future devices, and a device thereby fabricated.

摘要翻译： 一种用于通过使用具有不同有源区宽度的源极漏极过驱动电流元件（31,32,33）的测量技术来确定半导体器件（27）的有源区宽度（10）来制造闪速存储器件的方法，并且使用该方法 以确定器件（31,32,33）的有效区域宽度与绘制宽度之间的差异，并且使用差值来确定未来器件中的绘制宽度的实际宽度（10），以及由此制造的器件。

公开(公告)号：US06828623B1

公开(公告)日：2004-12-07

申请号：US10232487

申请日：2002-08-30

申请人： Xin Guo ,  Nian Yang ,  Zhigang Wang

发明人： Xin Guo ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L29788

CPC分类号： H01L29/518 ,  H01L21/28273 ,  H01L29/7885

摘要： A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including homogeneous oxynitride. The tunnel oxide dielectric layer separates a floating gate from a channel region that is formed between a source region and a drain region in a substrate. The flash memory cell further includes a dielectric layer that separates a control gate from the floating gate. In one case, the homogenous oxynitride is a defect free silicon nitride. The homogeneity of the oxynitride is due to the uniform distribution of nitride within the tunnel oxide dielectric layer. Further, the use of the homogeneous oxynitride can increase the dielectric constant and lower the barrier height of the tunnel oxide dielectric layer for increased performance. Also, the homogenous oxynitride supports source-side channel hot hole erasing in the flash memory cell.

摘要翻译： 具有均匀氧氮化物隧道电介质的存储器件。 具体地，本发明描述了一种闪存单元，其包括包括均匀氮氧化物的隧道氧化物介电层。 隧道氧化物电介质层将浮置栅极与形成在衬底中的源极区域和漏极区域之间的沟道区域分离。 闪存单元还包括将控制栅极与浮动栅极分离的介质层。 在一种情况下，均匀的氮氧化合物是无缺陷的氮化硅。 氧氮化物的均匀性是由于氮化物在隧​​道氧化物介电层内的均匀分布。 此外，为了提高性能，使用均匀的氮氧化物可以增加介电常数并降低隧道氧化物介电层的势垒高度。 此外，均匀的氮氧化物支持闪存单元中的源极侧通道热孔擦除。