公开(公告)号：US20230247841A1

公开(公告)日：2023-08-03

申请号：US17591174

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1159 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/42324

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

公开(公告)号：US11653501B2

公开(公告)日：2023-05-16

申请号：US17352339

申请日：2021-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L29/78 ,  H01L23/528 ,  H01L27/1159 ,  H01L27/11553 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11597 ,  H01L23/5283 ,  H01L27/1159 ,  H01L27/11553 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78391

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

公开(公告)号：US20230074585A1

公开(公告)日：2023-03-09

申请号：US17987066

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US20230049651A1

公开(公告)日：2023-02-16

申请号：US17401315

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chang Sun ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  TsuChing Yang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L27/11585 ,  H01L29/66

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

公开(公告)号：US20230038958A1

公开(公告)日：2023-02-09

申请号：US17669382

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Shyue Lai ,  Chien-Hao Huang ,  Chia-Yu Ling ,  Katherine H CHIANG ,  Chung-Te Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/1159 ,  H01L27/11597

Abstract: A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

公开(公告)号：US11575043B1

公开(公告)日：2023-02-07

申请号：US17383435

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Feng Yin ,  Chia-Jung Yu ,  Pin-Cheng Hsu ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L21/40 ,  H01L29/10 ,  H01L29/08 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.

公开(公告)号：US20220352184A1

公开(公告)日：2022-11-03

申请号：US17867998

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

IPC: H01L27/1159 ,  G11C11/22 ,  H01L27/12

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

公开(公告)号：US11450401B2

公开(公告)日：2022-09-20

申请号：US17108870

申请日：2020-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Katherine H. Chiang ,  Chien-Hao Huang ,  Cheng-Yi Wu ,  Chung-Te Lin

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/42 ,  G11C29/24 ,  G11C29/12

Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to determining that the CSP is solvable and has a solution satisfying the constraints, the at least one fail bit is repaired using the available repair resource in accordance with the solution of the CSP.

公开(公告)号：US20220278127A1

公开(公告)日：2022-09-01

申请号：US17464460

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chang Sun ,  Sheng-Chih Lai ,  Cheng-Jun Wu ,  Yu-Wei Jiang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11585 ,  H01L21/28 ,  H01L29/08

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

公开(公告)号：US20220028893A1

公开(公告)日：2022-01-27

申请号：US17121757

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Yi-Ching Liu ,  Chia-En Huang ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/11587 ,  G11C7/18 ,  G11C8/14 ,  H01L27/1159 ,  H01L23/522

Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device include a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.