公开(公告)号：US20140191802A1

公开(公告)日：2014-07-10

申请号：US13738450

申请日：2013-01-10

Applicant: Dan Li ,  Jinhua Ni

Inventor： Dan Li ,  Jinhua Ni

IPC: H03F3/217

CPC classification number: H03F3/2171 ,  H03F3/217

Abstract: An amplifier system may include a power stage having inputs for three different supply voltages and an output for coupling to a load, a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels, a monitor to provide a first control signal to the controller based on an input voltage signal, and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal.

Abstract translation: 放大器系统可以包括具有用于三个不同电源电压的输入和用于耦合到负载的输出的功率级，控制器以产生到功率级的控制信号，该功率级使功率级在施加到负载之间的输出电压变化 比三个不同的电压电平，基于输入电压信号向控制器提供第一控制信号的监视器，以及基于输出电压和输入信号的比较来向控制器提供第二控制信号的反馈系统。

公开(公告)号：US20140190542A1

公开(公告)日：2014-07-10

申请号：US14066129

申请日：2013-10-29

Applicant: William Allan LANE ,  Baoxing CHEN

Inventor： William Allan LANE ,  Baoxing CHEN

IPC: H01L35/32

CPC classification number: H01L35/32 ,  H01L27/16

Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.

Abstract translation: 集成电路可以包括在衬底上形成的衬底和介电层。 多个p型热电元件和多个n型热电元件可以设置在电介质层内。 p型热电元件和n型热电元件可以在p型和n型热电元件之间交替地串联连接。

公开(公告)号：US20140115195A1

公开(公告)日：2014-04-24

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US20140079079A1

公开(公告)日：2014-03-20

申请号：US13963260

申请日：2013-08-09

Applicant: Gerard MORA PUCHALT ,  Bhargav R. VYAS ,  Adrian W. SHERRY ,  Arvind MADAN

Inventor： Gerard MORA PUCHALT ,  Bhargav R. VYAS ,  Adrian W. SHERRY ,  Arvind MADAN

IPC: H04L12/931

CPC classification number: H04L49/405 ,  H03M1/1225 ,  H03M1/124

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract translation: 多通道系统，包括具有用于多个输入通道的输入的多路复用器，以及具有耦合到多路复用器的输入的多个输入的预充电缓冲器，以及耦合到多路复用器输出的输出。 多通道系统可以独立地存在，或者可以耦合到具有耦合到多路复用器的输出的输入的接收电路。 在一些情况下，接收电路是模数转换器。

公开(公告)号：US20140062596A1

公开(公告)日：2014-03-06

申请号：US13789449

申请日：2013-03-07

Applicant: Adam GLIBBERY

Inventor： Adam GLIBBERY

IPC: H03K3/36 ,  H03F3/45

CPC classification number: H03K3/36 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2203/45561 ,  H03F2203/45614 ,  H03F2203/45616 ,  H03F2203/45641 ,  H03F2203/45644 ,  H03F2203/45724 ,  H03F2203/45726 ,  H03K3/0231 ,  H03K4/06

Abstract: Embodiments of the present disclosure may provide a relaxation oscillator with improved performance against phase noise error. The phase noise error may be reduced from sources whose power is greater at lower frequencies. To reduce the noise error, the relaxation oscillator may include chopping in the charging current driver; chopping in the trigger level generator; and/or chopping in the currents that feed the cells. A chopped amplifier may be provided to perform chopping of the input signals.

Abstract translation: 本公开的实施例可以提供具有相对于相位噪声误差的改进性能的张弛振荡器。 在较低频率下功率较大的电源可能会降低相位噪声误差。 为了降低噪声误差，张弛振荡器可能包括在充电电流驱动器中的斩波; 在触发电平发生器中切断; 和/或在供给细胞的电流中切断。 可以提供斩波放大器来执行输入信号的斩波。

公开(公告)号：US20140002289A1

公开(公告)日：2014-01-02

申请号：US13841516

申请日：2013-03-15

Applicant: Dennis A. DEMPSEY

Inventor： Dennis A. DEMPSEY

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/1061 ,  H03M1/682 ,  H03M1/765

Abstract: Embodiments of the present invention may provide string DAC architecture with multiple stages for efficient resolution extension. A first stage may include an impedance string (e.g., resistor string). A second stage may include a switch network with each switch having more than two states (impedance values). A third stage may include a string DAC with an impedance string with a set of corresponding switches. In multi-channel embodiments, multiple second and third stages may be provided for each channel while sharing the same first stage (i.e., impedance string). Each second stage switch networks may be controlled based on the relationship between the different channels such as MSB values. Thus, the second stage switch networks may provide different impedance values to compensate for loading effects in multi-channel, multi-stage string DAC designs.

Abstract translation: 本发明的实施例可以提供具有用于有效分辨率扩展的多个级的串DAC架构。 第一级可以包括阻抗串（例如，电阻串）。 第二级可以包括具有多于两个状态（阻抗值）的每个开关的开关网络。 第三级可以包括具有一组相应开关的阻抗串的串DAC。 在多通道实施例中，可以为每个通道提供多个第二和第三级，同时共享相同的第一级（即，阻抗串）。 可以基于诸如MSB值之类的不同信道之间的关系来控制每个第二级交换机网络。 因此，第二级开关网络可以提供不同的阻抗值来补偿多通道，多级串型DAC设计中的负载效应。

公开(公告)号：US08589469B2

公开(公告)日：2013-11-19

申请号：US12008334

申请日：2008-01-10

Applicant: Andreas D. Olofsson ,  Baruch Yanovitch

Inventor： Andreas D. Olofsson ,  Baruch Yanovitch

IPC: G06F7/52

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3885

Abstract: Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations.

Abstract translation: 为数字处理器提供乘法引擎和乘法方法。 乘法引擎包括乘法器，每个乘法器接收第一操作数和第二操作数; 本地操作数寄存器，其具有用于保持各乘法器的第一操作数的位置; 耦合到本地操作数寄存器的第一操作数总线，用于将第一操作数从计算寄存器文件提供给本地操作数寄存器; 耦合到所述多个乘法器的第二操作数总线，以将所述第二操作数中的一个或多个从所述计算寄存器文件提供给各个乘法器; 以及控制单元，其响应于数字处理器指令将第一操作数从本地操作数寄存器提供给各个乘法器，以将第二操作数从计算寄存器文件提供给第二操作数总线上的相应乘法器，并将第一操作数乘以 各个乘法器中的相应的第二操作数，其中本地操作数寄存器中的第一操作数中的一个或多个在两个或多个乘法运算中由乘法器重新使用。

公开(公告)号：US09673696B2

公开(公告)日：2017-06-06

申请号：US14051702

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yanfeng Lu ,  Bin Shao

IPC: H02M1/36 ,  H02M3/155 ,  H02M3/07

CPC classification number: H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K2217/0081

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

公开(公告)号：US20160100243A1

公开(公告)日：2016-04-07

申请号：US14506062

申请日：2014-10-03

Applicant: Ulrik Sørensen Wismar ,  Sejun Kim

Inventor： Ulrik Sørensen Wismar ,  Sejun Kim

IPC: H04R1/10 ,  H03F3/181

CPC classification number: H04R1/1041 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/189 ,  H03F2203/45541 ,  H03F2203/45544 ,  H03F2203/45586 ,  H03F2203/45588 ,  H03F2203/45622 ,  H04R5/033 ,  H04R5/04 ,  H04R29/001

Abstract: A headset driver circuit is described which comprises a connector interface. The connector interface comprises a first terminal, a second terminal and a third terminal for establishing respective electrical connections to a first speaker, a microphone and a common ground node of a headphone, earphone or headset, respectively. A first power amplifier is coupled to the first terminal to supply a first audio output signal to the first speaker of the headset. A first switch arrangement comprises a first ground switch is configured for selectively connecting and disconnecting the second terminal and a ground node of the headset driver circuit. The headset driver circuit further comprises a second ground switch configured for selectively connecting and disconnecting the third terminal and the ground node. The headset driver circuit also comprises a differential preamplifier, e.g. a microphone preamplifier, configured to generate a microphone output voltage where the differential preamplifier comprises a first signal input coupled to the second terminal and a second signal input coupled to the third terminal of the connector interface. An error suppression circuit is configured to sense or sample a noise or error voltage at the second terminal when ground connected or the third terminal when ground connected. The error suppression circuit is further configured to add the sensed or sampled noise or error voltage to a predetermined DC bias voltage and generate an error compensated DC bias voltage for the ungrounded one of the second and third terminals of the connector interface.

Abstract translation: 描述了包括连接器接口的耳机驱动器电路。 连接器接口包括分别用于建立与耳机，耳机或耳机的第一扬声器，麦克风和公共接地节点的相应电连接的第一端子，第二端子和第三端子。 第一功率放大器耦合到第一端子，以向耳机的第一扬声器提供第一音频输出信号。 第一开关装置包括第一接地开关，其被配置用于选择性地连接和断开耳机驱动器电路的第二端子和接地节点。 头戴式耳机驱动器电路还包括被配置为选择性地连接和断开第三端子和接地节点的第二接地开关。 耳机驱动器电路还包括差分前置放大器，例如。 麦克风前置放大器，被配置为产生麦克风输出电压，其中所述差分前置放大器包括耦合到所述第二端子的第一信号输入和耦合到所述连接器接口的第三端子的第二信号输入。 误差抑制电路被配置为在接地时或第三端接地时，检测或采样第二端的噪声或误差电压。 误差抑制电路还被配置为将感测或采样的噪声或误差电压加到预定的直流偏置电压上，并为连接器接口的未接地的第二和第三端子产生误差补偿的直流偏置电压。

公开(公告)号：US20160049824A1

公开(公告)日：2016-02-18

申请号：US14461003

申请日：2014-08-15

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yosef Stein ,  Roman Trogan ,  Haim Primo

IPC: H02J7/02 ,  H04W72/04 ,  H04W4/00

CPC classification number: H02J7/025 ,  H02J50/20 ,  H02J50/23 ,  H02J50/90 ,  H04B5/0037 ,  H04B7/0617 ,  H04W4/70 ,  H04W16/28 ,  H04W52/04 ,  H04W64/00 ,  H04W84/18 ,  H04W88/16

Abstract: A wireless charging network system is disclosed that includes wirelessly charged sensor nodes. The wireless network system can include a gateway node configured to aggregate data from sensor nodes within a coverage area of the gateway node. The gateway node is further configured to wirelessly transmit power to the sensor nodes using a beamformed signal, wherein the gateway node adjusts the beamformed signal to maximize wireless power transfer to sensor nodes within each sector of the coverage area. Location information can be used to adjust the beamformed signal. For example, in various embodiments, the gateway node includes a beamformer sector profile table that defines channel adaptive beam profiles for the beamformed signal for each sector of the coverage area. The gateway node can use location information to define the beam profiles.

Abstract translation: 公开了一种包括无线充电传感器节点的无线充电网络系统。 无线网络系统可以包括被配置为从网关节点的覆盖区域内的传感器节点聚合数据的网关节点。 网关节点还被配置为使用波束形成的信号将功率无线传输到传感器节点，其中网关节点调整波束形成的信号以最大化对覆盖区域的每个扇区内的传感器节点的无线功率传输。 位置信息可用于调整波束形成信号。 例如，在各种实施例中，网关节点包括波束形成器扇区轮廓表，其为覆盖区域的每个扇区定义用于波束形成信号的信道自适应波束分布。 网关节点可以使用位置信息来定义波束轮廓。