公开(公告)号：US11954036B2

公开(公告)日：2024-04-09

申请号：US17985674

申请日：2022-11-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  James Michael O'Connor ,  Michael Mantor

IPC: G06F12/0862 ,  G06F8/41 ,  G06F9/52

CPC classification number: G06F12/0862 ,  G06F8/4442 ,  G06F9/52 ,  Y02D10/00

Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel that includes memory accesses for prefetching data for a processing kernel into a memory, and, subsequent to executing at least a portion of the prefetch kernel, executing the processing kernel where the processing kernel includes accesses to data that is stored into the memory resulting from execution of the prefetch kernel.

公开(公告)号：US20240112747A1

公开(公告)日：2024-04-04

申请号：US17957808

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Tahsin Askar ,  Naveen Davanam ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C29/10

CPC classification number: G11C29/10

Abstract: A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.

公开(公告)号：US20240112722A1

公开(公告)日：2024-04-04

申请号：US17957820

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  James R. Magro ,  Kedarnath Balakrishnan ,  Jing Wang

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40615 ,  G11C11/40622

Abstract: A memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. In response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. In response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.

公开(公告)号：US20240112720A1

公开(公告)日：2024-04-04

申请号：US17957788

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D Willey ,  Karthik Gopalakrishnan ,  Pradeep Jayaraman

IPC: G11C11/4076

CPC classification number: G11C11/4076

Abstract: A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming DQ signals.

公开(公告)号：US20240112392A1

公开(公告)日：2024-04-04

申请号：US17956567

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： David William John Pankratz ,  Konstantin I. Shkurko

IPC: G06T15/06 ,  G06T15/50

CPC classification number: G06T15/06 ,  G06T15/50

Abstract: Devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.

公开(公告)号：US20240111684A1

公开(公告)日：2024-04-04

申请号：US17957479

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sankaranarayanan Gurumurthy ,  Anil Harwani

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/601

Abstract: The disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. The method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240111683A1

公开(公告)日：2024-04-04

申请号：US17958179

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan

IPC: G06F12/0895

CPC classification number: G06F12/0895 ,  G06F2212/60

Abstract: A method includes, in a cache directory, storing a set of entries corresponding to one or more memory regions having a first region size when the cache directory is in a first configuration, and based on a workload sparsity metric, reconfiguring the cache directory to a second configuration. In the second configuration, each entry in the set of entries corresponds to a memory region having a second region size.

公开(公告)号：US20240111682A1

公开(公告)日：2024-04-04

申请号：US17957262

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Joseph Branover

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: Runtime flushing to persistency in heterogenous systems is described. In accordance with the described techniques, a system may include a persistent memory in electronic communication with at least one cache and a controller configured to command the at least one cache to flush dirty data to the persistent memory in response to a dirtiness of the at least one cache reaching a cache dirtiness threshold.

公开(公告)号：US20240111680A1

公开(公告)日：2024-04-04

申请号：US17957205

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Joseph Branover

IPC: G06F12/0868 ,  G06F12/084

CPC classification number: G06F12/0868 ,  G06F12/084 ,  G06F2212/1032

Abstract: Selecting between basic and global persistent flush modes is described. In accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while operating in the global persistent flush mode, and transmit a signal to switch control to an application to flush the dirty data from the at least one cache to the data fabric while operating in the basic persistent flush mode.

公开(公告)号：US20240111622A1

公开(公告)日：2024-04-04

申请号：US17957948

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Siddharth K. Shah ,  Vilas Sridharan ,  Amitabh Mehra ,  Anil Harwani ,  William Fischofer

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0721 ,  G06F11/079

Abstract: A disclosed method can include (i) reporting, by a microcontroller, detection of a violation of a physical infrastructure constraint to a machine check architecture, (ii) triggering, by the machine check architecture in response to the reporting, a machine-check exception such that the violation of the physical infrastructure constraint is recorded, and (iii) performing a corrective action based on the triggering of the machine-check exception. Various other apparatuses, systems, and methods are also disclosed.