公开(公告)号：US11989148B2

公开(公告)日：2024-05-21

申请号：US17548101

申请日：2021-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F13/42 ,  G06F1/06 ,  G06F1/08 ,  H03K3/037

CPC classification number: G06F13/42 ,  G06F1/06 ,  G06F1/08 ,  H03K3/037

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

公开(公告)号：US11979167B2

公开(公告)日：2024-05-07

申请号：US17876263

申请日：2022-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Sharad Gupta ,  Ankur Bal

IPC: H03M1/06

CPC classification number: H03M1/0665

Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

公开(公告)号：US20240128971A1

公开(公告)日：2024-04-18

申请号：US18481907

申请日：2023-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Sameer VASHISHTHA ,  Saiyid Mohammad Irshad RIZVI ,  Paras GARG

IPC: H03K17/56

CPC classification number: H03K17/56 ,  H03K2005/00078

Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

公开(公告)号：US11921537B2

公开(公告)日：2024-03-05

申请号：US17821398

申请日：2022-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Jeet Narayan Tiwari

IPC: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

CPC classification number: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

公开(公告)号：US11901919B2

公开(公告)日：2024-02-13

申请号：US17723225

申请日：2022-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Abhishek Jain ,  Sharad Gupta

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20240045458A1

公开(公告)日：2024-02-08

申请号：US18356818

申请日：2023-07-21

Applicant: STMicroelectronics International N.V.

Inventor： Zubair KHAN ,  Sandeep KAUSHIK

IPC: G05F1/575 ,  G05F1/46

CPC classification number: G05F1/575 ,  G05F1/468

Abstract: Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.

公开(公告)号：US11892360B2

公开(公告)日：2024-02-06

申请号：US17136240

申请日：2020-12-29

Applicant: STMicroelectronics International N.V.

Inventor： Atul Dwivedi ,  Pijush Kanti Panja

IPC: G01K7/00 ,  H03K17/60

CPC classification number: G01K7/00 ,  H03K17/60 ,  G01K2219/00

Abstract: Circuitry generates base-to-emitter voltages (Vbe1, Vbe2) of two BJTs biased at different current densities, a base-to-emitter voltage (Vbe) of a BJT biased so Vbe is complementary to absolute temperature and has a curved non-linearity across temperature, and base-to-emitter voltages (Vbe1_c, Vbe2_c) of two BJTs biased by a temperature independent constant current and a current proportional to absolute temperature so Vbe2_c−Vbe1_c has the same but opposite curved non-linearity across temperature as Vbe. A sampling circuit samples these voltages and provides them to inputs of a loop filter. Filter outputs are quantized to produce a bitstream. The sampling circuit: when the received bit of the bitstream is zero, causes integration of Vbe1−Vbe2 to produce a voltage proportional to absolute temperature (αΔVbe); and when the received bit of the bitstream is one, causes integration of Vbe2_c−Vbe_Vbe1_c to produce a negative voltage complementary to absolute temperature −Vbe_c without non-linearity across temperature.

公开(公告)号：US20240039545A1

公开(公告)日：2024-02-01

申请号：US18348899

申请日：2023-07-07

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL

IPC: H03L7/195 ,  H03L7/199 ,  H03K3/356

CPC classification number: H03L7/195 ,  H03L7/199 ,  H03K3/356026

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

公开(公告)号：US20240039537A1

公开(公告)日：2024-02-01

申请号：US18356146

申请日：2023-07-20

Applicant: STMicroelectronics International N.V.

Inventor： Manoj KUMAR ,  Paras GARG ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.