INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE

    公开(公告)号:US20250120114A1

    公开(公告)日:2025-04-10

    申请号:US18663238

    申请日:2024-05-14

    Abstract: An integrated circuit semiconductor device includes an active fin on a substrate, gate structures apart from one another on the active fin, an interlayer insulation layer to insulate the gate structures on the active fin, gate contacts apart from one another on the gate structures, active contacts apart from one another at both sides of the gate structures, the active contacts passing through the interlayer insulation layer and contacting the active fin, an etch stopping layer on the gate structures, the interlayer insulation layer, the gate contacts, and the active contacts, and diffusion break regions between the active contacts, the diffusion break regions being buried in gate trenches passing through the etch stopping layer and the interlayer insulation layer and in fin recesses cutting the active fin under the gate trenches.

    FLEXIBLE PRINTED CIRCUIT BOARD HAVING WATERPROOF STRUCTURE AND FOLDABLE ELECTRONIC DEVICE INCLUDING THE SAME

    公开(公告)号:US20250120015A1

    公开(公告)日:2025-04-10

    申请号:US18974667

    申请日:2024-12-09

    Abstract: An electronic device includes a first housing having a first through-hole, of which a first opening and a second opening are communicated with each other, and a second housing connected to the first housing to be rotatable. A flexible printed circuit board (FPCB) extends from the first housing to the second housing via the first through-hole. The FPCB includes a plurality of layers, a first sealing member disposed in the first through-hole and surrounding the FPCB, and a lamination part toward the first sealing member. A portion of a first layer and/or a second layer corresponding to the second lamination part includes at least one first valley extending from a surface that faces an adjacent layer in a lengthwise direction of the FPCB. The lamination part includes a first adhesive layer interposed between the first layer and the second layer and filling the at least one first valley.

    ELECTRONIC DEVICE AND SPATIAL REUSE CONTROL METHOD

    公开(公告)号:US20250119850A1

    公开(公告)日:2025-04-10

    申请号:US18984001

    申请日:2024-12-17

    Inventor: Junsu CHOI

    Abstract: An electronic device according to an embodiment may comprise: one or more wireless communication modules comprising communication circuitry configured to transmit/receive a wireless signal; at least one processor, comprising processing circuitry, operatively connected to the wireless communication module; and a memory electrically connected to at least one processor and storing instructions executable by the processor, wherein at least one processor, individually and/or collectively, is configured to execute the instructions and to: identify whether an SAR backoff regulation value is present for transmission power of the electronic device; set a spatial reuse parameter associated with the transmission power, on the basis of the SAR backoff regulation value; and perform communication on the basis of the spatial reuse parameter.

    METHOD AND DEVICE FOR CONTROLLING ENERGY USE IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20250119824A1

    公开(公告)日:2025-04-10

    申请号:US18908155

    申请日:2024-10-07

    Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. According to the disclosure, energy use per network slice can be efficiently controlled in a wireless communication system. A method performed by an SMF entity in a wireless communication system includes receiving, from an AMF entity, a first request message for a PDU session establishment including an S-NSSAI; determining whether the S-NSSAI is subject to energy control; and transmitting, to an NF entity, a second request message for an admission control including the S-NSSAI, in case that the S-NSSAI is subject to the energy control.

    METHOD AND DEVICE TO RECEIVE PHYSICAL DOWNLINK CONTROL CHANNEL

    公开(公告)号:US20250119248A1

    公开(公告)日:2025-04-10

    申请号:US18836207

    申请日:2023-02-16

    Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The present disclosure provides a method and device for receiving and transmitting information. According to an aspect of the present disclosure, a method for a network device is provided, which includes transmitting cell configuration information to a terminal device, wherein the cell configuration information includes a first downlink configuration information and a first uplink configuration information, and also includes at least one of a second uplink configuration information and a second downlink configuration information. The first uplink and the first downlink are related in frequency domain; wherein the second uplink satisfies at least one of the following conditions: the second uplink and the first downlink are related in frequency domain; the second uplink and the first uplink are related in frequency domain, wherein the second downlink satisfies at least one of the following conditions: the second downlink and the first downlink are related in frequency domain; the second downlink and the second uplink are related in frequency domain, and receiving, from the terminal device, an uplink signal transmitted by the terminal device based on the cell configuration information.

    HIGH-SENSITIVITY DELAY CELLS AND CIRCUITS OF DETECTING THRESHOLD VOLTAGE

    公开(公告)号:US20250119131A1

    公开(公告)日:2025-04-10

    申请号:US18626494

    申请日:2024-04-04

    Abstract: A circuit configured to detect a threshold voltage includes a first delay circuit, a second delay circuit and a controller. The first delay circuit has a first sensitivity to threshold voltage of a transistor. The first delay circuit may be configured to generate a first output signal delayed with respect to the input signal by a first delay time that changes depending on the digital control code. The second delay circuit has a second sensitivity that is higher than the first sensitivity. The second delay circuit may be configured to generate a second output signal delayed with respect to the input signal by a second delay time. The controller may compare the first and second output signals and may generate a digital output code corresponding to the digital control code when the first delay time is equal to the second delay time to indicate the threshold voltage of the transistor.

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