公开(公告)号：US07002842B2

公开(公告)日：2006-02-21

申请号：US10721184

申请日：2003-11-26

Applicant: Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek K. De

Inventor： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek K. De

IPC: G11C11/34

CPC classification number: H01L27/108 ,  G11C11/404

Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

公开(公告)号：US07001811B2

公开(公告)日：2006-02-21

申请号：US10750566

申请日：2003-12-31

Applicant: Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC: H01L21/336

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract translation: 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US06995605B2

公开(公告)日：2006-02-07

申请号：US10813169

申请日：2004-03-31

Applicant: Peter Hazucha ,  Jianping Xu ,  Gerhard Schrom ,  Tanay Karnik ,  Fabrice Paillet ,  Vivek K. De

Inventor： Peter Hazucha ,  Jianping Xu ,  Gerhard Schrom ,  Tanay Karnik ,  Fabrice Paillet ,  Vivek K. De

IPC: H03K5/00

CPC classification number: G06F1/305 ,  G06F1/28 ,  Y10T307/839

Abstract: A resonance suppression circuit is provided to suppress resonance on a power grid of a chip or die. The resonance suppression circuit may include a band-pass filter portion, a comparator portion, an amplification portion and a current dissipation portion. The band-pass filter portion may include an inverter coupled between two signal lines of the power grid. The comparator portion may sense voltage fluctuations at approximately the resonance frequency and trigger the current dissipation portion to turn ON and thereby change the frequency spectrum of the load current on the power grid to suppress the power grid resonance.

Abstract translation: 提供谐振抑制电路以抑制芯片或管芯的电网上的共振。 谐振抑制电路可以包括带通滤波器部分，比较器部分，放大部分和电流消耗部分。 带通滤波器部分可以包括耦合在电网的两个信号线之间的反相器。 比较器部分可以感测大致谐振频率处的电压波动，并且触发电流耗散部分导通，从而改变电网上的负载电流的频谱以抑制电网谐振。

公开(公告)号：US06849909B1

公开(公告)日：2005-02-01

申请号：US09677698

申请日：2000-09-28

Applicant: Rajendran Nair ,  Siva G. Narendra ,  Tanay Karnik ,  Vivek K. De

Inventor： Rajendran Nair ,  Siva G. Narendra ,  Tanay Karnik ,  Vivek K. De

IPC: H01L27/08 ,  H01L31/119 ,  H01L29/088 ,  H01L29/90

CPC classification number: H01L27/0811 ,  Y10S257/901

Abstract: A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.

Abstract translation: 描述了用于提供弱反型模式金属氧化物半导体（MOS）去耦电容器的方法和装置。 在一个实施例中，增强型p沟道MOS（PMOS）晶体管由其功能与常用功能不同的栅极材料构成。 在一个示例性实施方案中，使用铂硅酸盐（PtSi）。 在替代实施例中，可以通过修改衬底的掺杂剂水平来改变PMOS晶体管的阈值电压。 在任一实施例中，晶体管的平带幅度偏移用于构造晶体管的材料的变化。 当这种晶体管与连接到正电源电压的栅极引线连接，而其他引线连接到负（接地）电源电压时，会产生改进的去耦电容。

公开(公告)号：US06801465B2

公开(公告)日：2004-10-05

申请号：US10461293

申请日：2003-06-13

Applicant: Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

Inventor： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

IPC: G11C700

CPC classification number: G11C7/12

Abstract: An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

Abstract translation: 描述了具有耦合在第一位线和第二位线之间的多个存储单元的装置。 该装置还具有第一晶体管，其对第一位线进行预充电，并为多个存储单元中的任何一个提供从第一位线提取的一个或多个泄漏电流的第一电流。 该装置还具有第二晶体管，其对第二位线进行预充电并且为多个存储单元中的任一个提供从第二位线提取的一个或多个泄漏电流的第二电流供应。

公开(公告)号：US06784722B2

公开(公告)日：2004-08-31

申请号：US10267951

申请日：2002-10-09

Applicant: Stephen H. Tang ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

Inventor： Stephen H. Tang ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

IPC: G35F110

CPC classification number: G05F3/205 ,  H03K2217/0018

Abstract: A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.

Abstract translation: 提供一种具有差分差分放大器（DDA）的电路，差分差分放大器（DDA）具有第一和第二输入端以接收所需的体偏置信号;以及第三输入端，用于接收电源电压，所述DDA被配置为产生中间输出信号，所述中间输出信号耦合 到产生具有期望增益的输出信号的输出缓冲器，DDA具有第四输入，以使输出信号参考电源电压的变化。

公开(公告)号：US06763484B2

公开(公告)日：2004-07-13

申请号：US09894465

申请日：2001-06-28

Applicant: James W. Tschanz ,  Siva G. Narendra ,  Vivek K. De

Inventor： James W. Tschanz ,  Siva G. Narendra ,  Vivek K. De

IPC: G01R3128

CPC classification number: G01R31/318575 ,  H03K2217/0018

Abstract: A logic unit and method incorporating body biasing using scan chains, the logic unit comprising a functional unit block including a body and a scan chain, and a variable voltage source coupled to the scan chain to receive control signals from the scan chain and coupled to the body to provide a bias voltage to the body, and the method comprising identifying a preferred body bias voltage for a functional unit block having a body; and permanently programming a plurality of control signals coupled to a variable voltage source that provides the preferred body bias voltage to the body.

Abstract translation: 一种包括使用扫描链的主体偏置的逻辑单元和方法，所述逻辑单元包括包括主体和扫描链的功能单元块，以及耦合到所述扫描链的可变电压源，以从所述扫描链接收控制信号并耦合到所述扫描链 以向身体提供偏置电压，并且该方法包括识别具有身体的功能单元块的优选身体偏置电压; 并且永久地编程耦合到可变电压源的多个控制信号，所述可变电压源向身体提供优选的身体偏置电压。

公开(公告)号：US06707708B1

公开(公告)日：2004-03-16

申请号：US10241791

申请日：2002-09-10

Applicant: Atila Alvandpour ,  Dinesh Somasekhar ,  Steven K. Hsu ,  Ram K. Krishnamurthy ,  Vivek K. De

Inventor： Atila Alvandpour ,  Dinesh Somasekhar ,  Steven K. Hsu ,  Ram K. Krishnamurthy ,  Vivek K. De

IPC: G11C1100

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.

Abstract translation: 用于静态随机存取存储器的八单元，存储单元包括用于存储信息位的交叉耦合反相器，连接到局部位线的两个存取nMOSFET以访问所存储的信息位，以及两个nMOSFET，每个具有连接到地的栅极和 耦合到本地位线和交叉耦合的反相器，使得到达和从本地位线到不被读取的存储器单元的子阈值泄漏电流被平衡。

公开(公告)号：US06653866B2

公开(公告)日：2003-11-25

申请号：US10277009

申请日：2002-10-21

Applicant: Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

Inventor： Siva G. Narendra ,  Yibin Ye ,  Vivek K. De

IPC: H03K19096

CPC classification number: H03K19/0963 ,  H03K19/01728

Abstract: A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

公开(公告)号：US06608786B2

公开(公告)日：2003-08-19

申请号：US09823575

申请日：2001-03-30

Applicant: Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

Inventor： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

IPC: G11C700

CPC classification number: G11C7/12

Abstract: An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.