公开(公告)号：US20080194087A1

公开(公告)日：2008-08-14

申请号：US11729009

申请日：2007-03-28

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L21/3205 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L29/7834 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

公开(公告)号：US20080194072A1

公开(公告)日：2008-08-14

申请号：US11705655

申请日：2007-02-12

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

公开(公告)号：US20080191352A1

公开(公告)日：2008-08-14

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US20070249159A1

公开(公告)日：2007-10-25

申请号：US11409658

申请日：2006-04-24

申请人： Fang Tsai ,  I-I Chen ,  Zhen-Cheng Wu ,  Chih-Lung Lin ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

发明人： Fang Tsai ,  I-I Chen ,  Zhen-Cheng Wu ,  Chih-Lung Lin ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76843

摘要： A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.

摘要翻译： 提供了具有改进的低k电介质层和下层之间的粘附性的半导体结构及其形成方法。 所述半导体衬底包括半导体衬底上的电介质层，所述电介质层上的粘合层，其中所述粘合层包含初始子层上的过渡子层，并且其中所述过渡子层具有逐渐从 下部到上部。 在粘合层上形成低k电介质层。 在低k电介质层中形成镶嵌开口。 过渡子层的顶部具有与低k电介质层的组成基本相似的组成。 过渡子层的底部具有与初始子层的组成基本相似的组成。

公开(公告)号：US20070161230A1

公开(公告)日：2007-07-12

申请号：US11328596

申请日：2006-01-10

申请人： I-I Chen ,  Tien-I Bao ,  Shwang-Ming Cheng ,  Chen-Hua Yu

发明人： I-I Chen ,  Tien-I Bao ,  Shwang-Ming Cheng ,  Chen-Hua Yu

IPC分类号： H01L21/4763 ,  H01L21/469

CPC分类号： H01L21/76826 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

摘要： A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).

摘要翻译： 提供一种制造具有低k电介质层的半导体器件的方法。 一个实施方案包括在基底上形成介电层，其中该层包含分散在未固化的基质中的孔产生材料。 第二步骤包括通过用具有第一波长的辐射照射该层来在未固化的基质中形成孔。 在成孔之后，第三步骤包括通过以第二波长照射电介质来交联电介质，第二步小于第一波长。 在一个实施例中，照射波长包括紫外辐射。 实施方案可以进一步包括修复处理损伤，其中损伤包括悬挂键或硅烷醇形成。 修复包括在含碳环境中退火，例如C 2 H 4 H 3，C 3 H 6， 或六甲基二硅氮烷（HMDS）。

公开(公告)号：US07232362B2

公开(公告)日：2007-06-19

申请号：US10964145

申请日：2004-10-12

申请人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： B24B1/00

CPC分类号： H01L21/3212 ,  B24B37/042

摘要： A chemical-mechanical polishing (CMP) process for the manufacturing of semiconductor devices is disclosed. The process includes removing a first portion of a first layer of interconnect materials using a first platen and a first slurry, removing a second portion of the first layer using a second platen and a second slurry, removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry, and removing a second portion of the second layer using a third platen and a fourth slurry.

摘要翻译： 公开了用于制造半导体器件的化学机械抛光（CMP）工艺。 该方法包括使用第一压板和第一浆料去除第一层互连材料的第一部分，使用第二压板和第二浆料除去第一层的第二部分，去除第二层的第一部分 使用第二压板和第三浆料的互连材料，以及使用第三压板和第四浆料除去第二层的第二部分。

公开(公告)号：US07187084B2

公开(公告)日：2007-03-06

申请号：US10760905

申请日：2004-01-20

申请人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/76807

摘要： A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a composite etch stop layer over the lower intermetal dielectric layer and the exposed conductive structure; the composite etch stop layer comprising a first lower sub-layer and a second upper sub-layer, an upper intermetal dielectric layer over the composite etch stop layer, a trench interconnection opening forming within the upper intermetal dielectric layer and the composite etch stop layer, the trench interconnection opening exposing the conductive structure, a barrier metal layer at least lining the trench interconnection opening. and a conductor plug within the trench interconnection opening, contacting the conductive structure. The upper surface of the barrier metal layer is coplanar with the upper surface of the conductor plug.

摘要翻译： 提供一种镶嵌结构，其包括基底，在该基底上的下部金属间电介质层，该下部金属间电介质层内的暴露的导电结构，该下部金属间介电层上的复合蚀刻停止层和该暴露的导电结构; 所述复合蚀刻停止层包括第一下部子层和第二上部子层，复合蚀刻停止层上方的上部金属间介电层，在上部金属间介电层和复合蚀刻停止层中形成的沟槽互连开口， 所述沟槽互连开口暴露所述导电结构，至少衬垫所述沟槽互连开口的阻挡金属层。 以及沟槽互连开口内的导体插头，与导电结构接触。 阻挡金属层的上表面与导体插塞的上表面共面。

公开(公告)号：US20060121717A1

公开(公告)日：2006-06-08

申请号：US11001003

申请日：2004-12-02

申请人： Chen-Hua Yu ,  Chung-Shi Liu

发明人： Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76828 ,  H01L21/76832 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/05552

摘要： Bonding structure and method of fabricating the same. The bonding structure of the invention includes an insulating layer having at least one metal segment formed thereon and a bonding pad over the metal segment, wherein the bonding pad is substantially surrounded by a first passivation layer comprising a first atomic hydrogen penetrable layer.

摘要翻译： 粘结结构及其制造方法。 本发明的接合结构包括其上形成有至少一个金属段的绝缘层和金属段上的接合焊盘，其中焊盘基本上由包括第一原子氢穿透层的第一钝化层包围。

公开(公告)号：US20050250332A1

公开(公告)日：2005-11-10

申请号：US10840049

申请日：2004-05-05

申请人： Boq-Kang Hwu ,  Chung-Shi Liu ,  Chen-Hua Yu

发明人： Boq-Kang Hwu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L21/321 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01L21/76838 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873

摘要： A method for reducing or preventing contamination or oxidation of copper surfaces included in semiconductor process wafers including providing a semiconductor wafer including copper features having newly formed process surfaces following a semiconductor manufacturing process forming the newly formed process surfaces; exposing the process surfaces to an alkaline solution for a period of time sufficient to chemically modify the newly formed process surfaces prior to substantial exposure of the process surfaces to a contaminating or oxidizing atmosphere; and, placing the semiconductor wafer in a semiconductor wafer holding environment in queue for subsequent semiconductor manufacturing processes.

摘要翻译： 一种用于减少或防止包含在半导体工艺晶片中的铜表面的污染或氧化的方法，包括：提供包含具有新形成的工艺表面的铜特征的半导体晶片; 将工艺表面暴露于碱性溶液一段足以在将工艺表面大量暴露于污染或氧化气氛之前化学改性新形成的工艺表面的时间; 并且将半导体晶片置于半导体晶片保持环境中，用于随后的半导体制造工艺。

公开(公告)号：US06958291B2

公开(公告)日：2005-10-25

申请号：US10654757

申请日：2003-09-04

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76846

摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。