公开(公告)号：US20230217836A1

公开(公告)日：2023-07-06

申请号：US17566812

申请日：2021-12-31

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Hao Tang ,  Theodoros E Standaert

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.

公开(公告)号：US11682558B2

公开(公告)日：2023-06-20

申请号：US17481981

申请日：2021-09-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Ashim Dutta ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/31111

Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

公开(公告)号：US11681213B2

公开(公告)日：2023-06-20

申请号：US16282005

申请日：2019-02-21

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Luciana Meli Thompson ,  Ashim Dutta ,  Ekmini A. De Silva

IPC: G03F7/075 ,  G03F1/22 ,  H01L21/308

CPC classification number: G03F1/22 ,  G03F7/0757 ,  H01L21/3081

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

公开(公告)号：US20230172073A1

公开(公告)日：2023-06-01

申请号：US17539316

申请日：2021-12-01

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Lili Cheng ,  Chih-Chao Yang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in the substrate. A metal line on a metal interconnect of the non-memory area interconnect structure is formed. A first dielectric layer on exposed surfaces of the non-memory area is formed. A hardmask is formed on the dielectric layer. A second dielectric layer is formed on exposed surfaces of the memory area. A bottom metal contact is formed in a trench, a bottom surface of the bottom metal contact on a top surface of a first metal interconnect of the memory area interconnect structure. A memory element stack pillar is formed on the bottom metal contact.

公开(公告)号：US20230170266A1

公开(公告)日：2023-06-01

申请号：US17536228

申请日：2021-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Ruturaj Nandkumar Pujari ,  Saumya Sharma ,  Chih-Chao Yang

IPC: H01L21/66 ,  H01L23/544 ,  G01B11/27 ,  G01R1/073

CPC classification number: H01L22/32 ,  H01L23/544 ,  G01B11/272 ,  G01R1/073 ,  H01L2223/54426

Abstract: A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.

公开(公告)号：US20230147958A1

公开(公告)日：2023-05-11

申请号：US17453841

申请日：2021-11-06

Applicant: International Business Machines Corporation

Inventor： Dexin Kong ,  Ekmini Anuja De Silva ,  Ashim Dutta ,  Daniel Schmidt

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1675

Abstract: A high-density resistive random-access memory array with self-aligned bottom electrode contact includes a plurality of electrically conductive structures embedded in an interconnect dielectric material layer, a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures with the bottom electrode above an electrically conductive structure being separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, the bottom electrode having a semi-circular shape. The array further includes a resistive random-access memory pillar disposed above the bottom electrode.

公开(公告)号：US20230098122A1

公开(公告)日：2023-03-30

申请号：US17489888

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Lili Cheng ,  Chih-Chao Yang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A semiconductor device, such as an MRAM device, includes a stepped contact within a memory region that has a greater number of different contact structures (i.e., contact structures formed in different fabrication stages) relative to a logic region contact. The stepped contact includes a lower stepped contact and an upper stepped contact. The inclusion of the lower stepped contact allows for a relatively shorter upper stepped contact compared to the logic region contact. The stepped contact may allow the use of a multi-layer encapsulation spacer upon the sidewalls of a memory cell that fill out tight spacing therebetween, which may decrease the propensity of void formation and resulting shorting between neighboring memory cell features.

公开(公告)号：US11437083B2

公开(公告)日：2022-09-06

申请号：US17168891

申请日：2021-02-05

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Eric Raymond Evarts

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A magnetoresistive random-access memory (MRAM) device includes a first cell selectively connected to a first bit line and a second cell selectively connected to a second bit line. The MRAM device further includes a shared transistor connected to the first cell and connected to the second cell. The MRAM device further includes a first selector device and a second selector device. The first selector device is configured to permit current to flow through the first cell to the shared transistor when a voltage applied to the first selector device is larger than a threshold activation voltage. The second selector device is configured to permit current to flow through the second cell to the shared transistor when a voltage applied to the second selector device is larger than a threshold activation voltage. The MRAM cell further includes a word line connected to a gate of the shared transistor.

公开(公告)号：US11251368B2

公开(公告)日：2022-02-15

申请号：US16852997

申请日：2020-04-20

Applicant: International Business Machines Corporation

Inventor： Tianji Zhou ,  Saumya Sharma ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method includes forming a first metallization layer containing a first metal-containing line and a second metal-containing line disposed in a first interlevel dielectric layer. The first metal-containing line includes a first conductive metal and the second metal-containing line includes a second conductive metal. The first metal-containing line and the second metal-containing line are recessed to below a top surface of the interlevel dielectric layer. A metal-containing cap protection layer is deposited in a recessed portion of the first metal-containing line and the second metal-containing line. The metal-containing cap protection layer includes a third conductive metal which is different than the first conductive metal and the second conductive metal.

公开(公告)号：US11205678B2

公开(公告)日：2021-12-21

申请号：US16780684

申请日：2020-02-03

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Dominik Metzler

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.