公开(公告)号：US07531407B2

公开(公告)日：2009-05-12

申请号：US11488242

申请日：2006-07-18

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/8234

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。 例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。 在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。 通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。 半导体衬底可以是SOI（绝缘体上硅）结构。

公开(公告)号：US20080301597A1

公开(公告)日：2008-12-04

申请号：US11754947

申请日：2007-05-29

申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

IPC分类号： G06F17/50

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

公开(公告)号：US20080105969A1

公开(公告)日：2008-05-08

申请号：US11965445

申请日：2007-12-27

申请人： Louis Hsu ,  Rajiv Joshi ,  Jack Mandelman

发明人： Louis Hsu ,  Rajiv Joshi ,  Jack Mandelman

IPC分类号： H01L23/36 ,  H01L21/58

CPC分类号： H01L23/3677 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S438/928 ,  Y10S438/96 ,  Y10S438/977 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

摘要翻译： 一种制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有热膨胀系数的第一材料（ CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。

公开(公告)号：US20080092367A1

公开(公告)日：2008-04-24

申请号：US11968896

申请日：2008-01-03

申请人： Louis Hsu ,  Lawrence Clevenger ,  Timothy Dalton ,  Carl Radens ,  Keith Wong ,  Chih-Chao Yang

发明人： Louis Hsu ,  Lawrence Clevenger ,  Timothy Dalton ,  Carl Radens ,  Keith Wong ,  Chih-Chao Yang

IPC分类号： H01H11/00 ,  H01F41/04

CPC分类号： H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

摘要： A method of fabricating a MEMS switch having a free moving inductive element within in micro-cavity guided by at least one inductive coil. The switch consists of an upper inductive coil at one end of a micro-cavity; optionally, a lower inductive coil; and a free-moving inductive element preferably made of magnetic material. The coils are provided with an inner permalloy core. Switching is achieved by passing a current through the upper coil, inducing a magnetic field unto the inductive element. The magnetic field attracts the free-moving inductive element upwards, shorting two open conductive wires, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the conductive wires open. When the chip is not mounted with the correct orientation, the lower coil pulls the free-moving inductive element back at its original position.

摘要翻译： 一种制造具有由至少一个感应线圈引导的微腔内的自由运动的感应元件的MEMS开关的方法。 开关由微腔一端的上感应线圈组成; 可选地，下感应线圈; 以及优选由磁性材料制成的自由移动的电感元件。 线圈设有内坡道合金芯。 通过使电流通过上部线圈，从而产生电感元件的磁场来实现切换。 磁场向上吸引自由移动的感应元件，短路两根开放的导线，闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且导线打开。 当芯片没有以正确的方向安装时，下线圈将自由移动的感应元件拉回其原始位置。

公开(公告)号：US20080026512A1

公开(公告)日：2008-01-31

申请号：US11867213

申请日：2007-10-04

申请人： RAJIV JOSHI ,  Louis Hsu ,  Oleg Gluschenkov

发明人： RAJIV JOSHI ,  Louis Hsu ,  Oleg Gluschenkov

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US20080020488A1

公开(公告)日：2008-01-24

申请号：US11488242

申请日：2006-07-18

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。 例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。 在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。 通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。 半导体衬底可以是SOI（绝缘体上硅）结构。

公开(公告)号：US20070257314A1

公开(公告)日：2007-11-08

申请号：US11775607

申请日：2007-07-10

申请人： RAJIV JOSHI ,  Louis Hsu ,  OLEG GLUSCHENKOV

发明人： RAJIV JOSHI ,  Louis Hsu ,  OLEG GLUSCHENKOV

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

公开(公告)号：US20070254464A1

公开(公告)日：2007-11-01

申请号：US11413010

申请日：2006-04-28

申请人： Brian Greene ,  Louis Hsu ,  Jack Mandelman ,  Chun-Yung Sung

发明人： Brian Greene ,  Louis Hsu ,  Jack Mandelman ,  Chun-Yung Sung

IPC分类号： H01L21/28

CPC分类号： H01L29/458 ,  H01L29/66628 ,  H01L29/66772

摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

摘要翻译： 一种降低绝缘体上硅器件上的接触电阻的方法（和系统），包括控制器件源极 - 漏极区域中的硅化物深度。

公开(公告)号：US20070212870A1

公开(公告)日：2007-09-13

申请号：US11308220

申请日：2006-03-13

申请人： Chih-Chao Yang ,  Louis Hsu

发明人： Chih-Chao Yang ,  Louis Hsu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.

摘要翻译： 提供一种互连结构，其包括能够在电迁移（EM）故障之后避免突然断路的障碍物冗余特征以及其形成方法。 根据本发明，阻挡冗余特征位于互连结构内的预选位置，包括在宽线区域，细线区域或其任何组合中。 阻挡层冗余特征包括导电材料，其位于导电线的导电线扩散阻挡层和上覆通孔的通孔扩散阻挡层之间并与之接触。 本发明的阻挡 - 冗余特征的存在在沿着导电线的侧壁的通孔的侧壁和导电线扩散阻挡层之间形成通路扩散阻挡层之间的电路径。 由本发明的障碍物冗余特征产生的该电路径可以避免由于通孔底部的EM故障导致的突然开路。 在互连结构内部存在本发明的障碍物冗余特征为芯片更换或系统操作提供足够的时间。

公开(公告)号：US20070210411A1

公开(公告)日：2007-09-13

申请号：US11372334

申请日：2006-03-09

申请人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。