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    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
    133.
    发明申请
    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE 有权

    公开(公告)号：US20250077416A1

    公开(公告)日：2025-03-06

    申请号：US18781838

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Huai-Yuan Tseng ,  Xiangyu Tang ,  Eric N. Lee ,  Haibo Li ,  Kishore Kumar Muchherla ,  Akira Goda

    IPC: G06F12/02

    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

    MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS
    135.
    发明申请
    MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS 有权

    公开(公告)号：US20240413145A1

    公开(公告)日：2024-12-12

    申请号：US18808990

    申请日：2024-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

    IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

    PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING
    138.
    发明公开
    PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING 审中-公开

    公开(公告)号：US20240311057A1

    公开(公告)日：2024-09-19

    申请号：US18606670

    申请日：2024-03-15

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard ,  Kishore K. Muchherla ,  Hong Lu ,  Xiangang Luo ,  Akira Goda

    IPC: G06F3/06

    CPC classification number: G06F3/0679 ,  G06F3/0614 ,  G06F3/0659

    Abstract: A method can comprise receiving data corresponding to a sequence of write commands to write the data to a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block having a first programming characteristic; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block having a second programming characteristic. The method can further comprise writing data sequentially to the first erase blocks of the plurality of strings and the second erase blocks of the plurality of strings in an interleaved manner by: writing a first portion of the data to one or more first erase blocks of the plurality of strings; and writing, subsequent to writing the first portion of the data to the one or more first erase blocks, a second portion of the data to one or more second erase blocks of the plurality of strings.

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