公开(公告)号：US11735261B2

公开(公告)日：2023-08-22

申请号：US17544679

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0007 ,  H10B63/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/884 ,  H10N70/8825 ,  H10N70/8828 ,  G11C2013/0073 ,  G11C2213/52

Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

公开(公告)号：US11716861B2

公开(公告)日：2023-08-01

申请号：US17122464

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  H10N70/023 ,  H10N70/041 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2013/0083 ,  G11C2213/71

Abstract: Electrically formed memory arrays, and methods of processing the same are described herein. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a first plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, a storage element material formed around each respective one of the first plurality of conductive extensions, a second plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a plurality of single element materials formed around each respective one of the second plurality of conductive extensions.

公开(公告)号：US20230027799A1

公开(公告)日：2023-01-26

申请号：US17881274

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

公开(公告)号：US20220366974A1

公开(公告)日：2022-11-17

申请号：US17816612

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C13/00

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

公开(公告)号：US11468930B2

公开(公告)日：2022-10-11

申请号：US17193227

申请日：2021-03-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Fabio Pellizzer

IPC: G11C8/10 ,  G11C5/06 ,  G11C5/02

Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

公开(公告)号：US11374059B2

公开(公告)日：2022-06-28

申请号：US16892459

申请日：2020-06-04

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L45/00 ,  H01L49/02

Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.

公开(公告)号：US11152065B2

公开(公告)日：2021-10-19

申请号：US16863175

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

IPC: G11C13/02 ,  G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

公开(公告)号：US11018300B2

公开(公告)日：2021-05-25

申请号：US16665955

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

公开(公告)号：US10937829B2

公开(公告)日：2021-03-02

申请号：US16550532

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

公开(公告)号：US20210043685A1

公开(公告)日：2021-02-11

申请号：US16534952

申请日：2019-08-07

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Anna Maria Conti

IPC: H01L27/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L45/00 ,  H01L27/11514 ,  H01L23/528

Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.