公开(公告)号：US20240013822A1

公开(公告)日：2024-01-11

申请号：US17861231

申请日：2022-07-10

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Marco Sforzin

IPC: G11C7/12 ,  G11C7/10 ,  G06F11/07

CPC classification number: G11C7/12 ,  G11C7/1069 ,  G06F11/0793 ,  G06F11/073

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a method can include receiving a command to perform a precharge operation on a set of memory cells in a memory device. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The method can further include accessing one or more sets of bits in a mode register. The one or more sets of bits in the mode register indicate address locations of the plurality of sets of memory cells to disable the flip on precharge operation. The method can further include performing the precharge operation on the set of memory cells. The flip on precharge operation associated with the precharge operation can be disabled for those sets of the plurality of sets of memory cells whose address locations are in the mode register.

公开(公告)号：US20240004760A1

公开(公告)日：2024-01-04

申请号：US18216160

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US11853606B2

公开(公告)日：2023-12-26

申请号：US17492309

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673 ,  G11C13/0069 ,  G11C2213/30

Abstract: The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.

公开(公告)号：US11797717B2

公开(公告)日：2023-10-24

申请号：US16765224

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolo Izzo

IPC: G06F21/85 ,  G06F12/02 ,  G06F21/60 ,  G06F21/79 ,  G06F12/14

CPC classification number: G06F21/85 ,  G06F12/0246 ,  G06F12/1408 ,  G06F21/602 ,  G06F21/79

Abstract: The present disclosure relates to apparatuses and methods for memory management. The disclosure further relates to an interface protocol for flash memory devices including at least a memory array and a memory controller coupled to the memory array.
A host device is coupled to the memory device through a communication channel and a hardware and/or software full encryption-decryption scheme is adopted in the communication channel for data, addresses and commands exchanged between the host device and the memory array.

公开(公告)号：US11742047B2

公开(公告)日：2023-08-29

申请号：US17361419

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Christophe Vincent Antoine Laurent

IPC: G11C29/42 ,  G11C29/56 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C29/56016

Abstract: Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector.

公开(公告)号：US20230016520A1

公开(公告)日：2023-01-19

申请号：US17861233

申请日：2022-07-10

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

公开(公告)号：US20220359034A1

公开(公告)日：2022-11-10

申请号：US17874897

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Stephen S. Pawlowski

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/10 ,  G11C29/44 ,  H03M13/27

Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.

公开(公告)号：US11335408B2

公开(公告)日：2022-05-17

申请号：US17200385

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/28 ,  G11C7/14 ,  G11C11/24 ,  G11C7/06 ,  G11C11/404 ,  G11C13/00 ,  G11C11/56

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

公开(公告)号：US20220130461A1

公开(公告)日：2022-04-28

申请号：US17518176

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/32

Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.

公开(公告)号：US11282574B2

公开(公告)日：2022-03-22

申请号：US17062127

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

IPC: G11C7/10 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/56 ,  G11C7/06

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.