公开(公告)号：US20210365268A1

公开(公告)日：2021-11-25

申请号：US16878226

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/1045 ,  G06F12/0868 ,  G06F13/16

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US10942652B2

公开(公告)日：2021-03-09

申请号：US16433803

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G06F15/78 ,  G11C29/28 ,  G11C29/26 ,  G11C5/02

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.

公开(公告)号：US20210004237A1

公开(公告)日：2021-01-07

申请号：US17027431

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US10796736B2

公开(公告)日：2020-10-06

申请号：US16101165

申请日：2018-08-10

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Troy A. Manning

IPC: G11C8/00 ,  G11C7/10 ,  H03K19/173 ,  G06F13/12 ,  G11C11/408 ,  G11C8/12 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US20200152246A1

公开(公告)日：2020-05-14

申请号：US16741466

申请日：2020-01-13

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G06F3/06 ,  G11C7/10 ,  G11C7/06 ,  H03K19/00 ,  H03K19/1776 ,  G06F7/523 ,  G11C11/4091 ,  G11C11/4074 ,  G06F12/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US20190180796A1

公开(公告)日：2019-06-13

申请号：US16277472

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Troy A. Manning

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4091

CPC classification number: G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/1673 ,  G11C11/4091 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

公开(公告)号：US20180358058A1

公开(公告)日：2018-12-13

申请号：US16105543

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C15/04 ,  G11C7/12 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4091

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

公开(公告)号：US20180350413A1

公开(公告)日：2018-12-06

申请号：US16101165

申请日：2018-08-10

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Troy A. Manning

IPC: G11C7/10 ,  H03K19/173 ,  G06F13/12 ,  G06F12/02 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US20170358332A1

公开(公告)日：2017-12-14

申请号：US15688545

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C7/10 ,  G11C15/00 ,  G06F12/00 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

公开(公告)号：US09704540B2

公开(公告)日：2017-07-11

申请号：US14713724

申请日：2015-05-15

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Richard C. Murphy

IPC: G11C29/00 ,  G11C7/06 ,  G06F11/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/4091

CPC classification number: G11C7/06 ,  G06F11/10 ,  G06F11/1048 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.