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公开(公告)号:US07573469B2
公开(公告)日:2009-08-11
申请号:US11041454
申请日:2005-01-25
申请人: Shunpei Yamazaki , Jun Koyama
发明人: Shunpei Yamazaki , Jun Koyama
IPC分类号: G09G3/20
CPC分类号: H01L27/3276 , G02F1/13454 , G02F2001/13456 , H01L2251/5315
摘要: In a display device having driving circuits formed on the same substrate where pixels are formed, the lateral frame area of the display device is reduced. A gate signal line driving circuit is placed in parallel with a source signal line driving circuit, so that no driving circuits are provided in at least two opposing directions out of four directions with respect to a pixel region. With the above-described structure, the area the gate signal line driving circuit occupies in prior art is removed to reduce the width (side to side) of the display device. Therefore a display device that has a small frame area in the lateral direction can be provided.
摘要翻译: 在具有形成在形成有像素的同一基板上的驱动电路的显示装置中,显示装置的横向框架区域减小。 栅极信号线驱动电路与源极信号线驱动电路并联放置,使得在相对于像素区域的四个方向上的至少两个相对的方向上不设置驱动电路。 利用上述结构,去除了现有技术中栅极信号线驱动电路占据的面积以减小显示装置的宽度(一侧到另一侧)。 因此,可以提供在横向上具有小框架区域的显示装置。
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公开(公告)号:US20090072757A1
公开(公告)日:2009-03-19
申请号:US12238035
申请日:2008-09-25
申请人: Shunpei Yamazaki , Mitsuaki Osame , Jun Koyama
发明人: Shunpei Yamazaki , Mitsuaki Osame , Jun Koyama
IPC分类号: H05B37/02
CPC分类号: H05B33/08 , H01L27/124 , H05B33/0812 , H05B33/0896
摘要: The present invention is characterized in that a transistor with its L/W set to 10 or larger is employed, and that |VDS| of the transistor is set equal to or larger than 1 V and equal to or less than |VGS−Vth|. The transistor is used as a resistor so that the resistance of a light emitting element can be held by the transistor. This slows down an increase in internal resistance of the light emitting element and the resultant current value reduction. Accordingly, a change with time in light emission luminance is reduced and the reliability is improved.
摘要翻译: 本发明的特征在于采用其L / W设定为10以上的晶体管,| VDS | 被设定为等于或大于1V且等于或小于| VGS-Vth |。 晶体管用作电阻器,使得发光元件的电阻可以由晶体管保持。 这减慢了发光元件的内阻的增加和合成的电流值的降低。 因此,降低发光亮度随时间的变化,提高可靠性。
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公开(公告)号:US20090057670A1
公开(公告)日:2009-03-05
申请号:US12193900
申请日:2008-08-19
IPC分类号: H01L21/77 , H01L27/088
CPC分类号: H01L27/124 , G02F1/13454 , G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/136277 , G02F1/1368 , G02F2001/136245 , H01L27/1237 , H01L27/1255 , H01L27/3244 , H01L29/78633 , H01L29/78645
摘要: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.
摘要翻译: 本文公开了一种具有高可靠性的半导体器件,其具有根据所需电路性能布置的适当结构的TFT。 半导体在同一衬底上具有驱动电路和像素部分。 其特征在于,在与遮光膜形成在同一层上的第一电极和由与漏区相同组成的半导体膜形成的第二电极之间形成存储电容,并且去除第一基底绝缘膜 在存储电容的一部分处,使得第二基极绝缘膜用作存储电容的电介质。 该结构在小面积上提供了大的存储电容。
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公开(公告)号:US07486344B2
公开(公告)日:2009-02-03
申请号:US11679936
申请日:2007-02-28
申请人: Shunpei Yamazaki , Jun Koyama , Hideomi Suzawa , Koji Ono , Tatsuya Arao
发明人: Shunpei Yamazaki , Jun Koyama , Hideomi Suzawa , Koji Ono , Tatsuya Arao
IPC分类号: G02F1/136
CPC分类号: H01L27/1214 , G02F1/13454 , G02F1/1368 , H01L27/124 , H01L27/127
摘要: A highly reliable semiconductor display device is provided. The semiconductor display device has a channel forming region, an LDD region, and a source region and a drain region in a semiconductor layer, and the LDD region overlaps with a first gate electrode, sandwiching a gate insulating film.
摘要翻译: 提供了高度可靠的半导体显示装置。 半导体显示装置在半导体层中具有沟道形成区域,LDD区域,源极区域和漏极区域,并且LDD区域与第一栅极电极重叠,夹着栅极绝缘膜。
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公开(公告)号:US07485896B2
公开(公告)日:2009-02-03
申请号:US11717677
申请日:2007-03-14
申请人: Shunpei Yamazaki , Jun Koyama
发明人: Shunpei Yamazaki , Jun Koyama
IPC分类号: H01L27/15
CPC分类号: H01L29/78696 , H01L21/3226 , H01L27/124 , H01L27/1288 , H01L27/3262 , H01L27/3276 , H01L29/6675 , H01L29/66757 , H01L29/78603 , H01L29/78636 , H01L29/78645 , H01L29/78648
摘要: An object of the invention is to provide a technique for improving the characteristics of a TFT and realizing an optimum structure of the TFT for the driving conditions of a pixel section and a driving circuit by a small number of photo masks. Therefore, a light emitting device has a semiconductor film, a first electrode and a first insulating film nipped between the semiconductor film and the first electrode. Further, the light emitting device has a second electrode and a second insulating film nipped between the semiconductor film and the second electrode. The first and second electrodes are overlapped with each other through a channel forming area arranged in the semiconductor film. In the case of a TFT in which a reduction in off-electric current is considered important in comparison with an increase in on-electric current, a constant voltage (common voltage) is applied to the first electrode at any time. In the case of a TFT in which the increase in on-electric current is considered important in comparison with the reduction in off-electric current, the same voltage is applied to the first and second electrodes.
摘要翻译: 本发明的目的是提供一种用于改善TFT的特性并通过少量光掩模实现用于像素部分和驱动电路的驱动条件的TFT的最佳结构的技术。 因此,发光器件具有夹在半导体膜和第一电极之间的半导体膜,第一电极和第一绝缘膜。 此外,发光器件具有夹在半导体膜和第二电极之间的第二电极和第二绝缘膜。 第一和第二电极通过布置在半导体膜中的沟道形成区彼此重叠。 在与导通电流的增加相比,将电流降低视为重要的TFT的情况下,在任何时候都向第一电极施加恒定电压(公共电压)。 在与减少截止电流相比较,导通电流的增加被认为是重要的TFT的情况下,对第一和第二电极施加相同的电压。
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公开(公告)号:US07471368B2
公开(公告)日:2008-12-30
申请号:US11072455
申请日:2005-03-07
申请人: Shunpei Yamazaki , Jun Koyama
发明人: Shunpei Yamazaki , Jun Koyama
IPC分类号: G02F1/1345
CPC分类号: G02F1/13452 , G02F1/1345
摘要: To provide means for resolving a problem in which in steps of connecting a panel array substrate and a stick substrate, connection failure is enhanced and reliability is deteriorated by a positional shift caused in connecting operation and a positional shift caused by shrinkage of te substrate, a shape of a total of a stick substrate 103 is constituted by a rectangular shape (lx1×ly1) and contiguous electrode pads are annaged to shirt by Ts in Y-direction by which lead wirings of the panel array substrate and lead wirings of the stick substrate can be connected with high accuracy and an electrooptical device having high yield and excellent display characteristic is provided.
摘要翻译: 为了提供解决连接面板阵列基板和棒基板的步骤的问题的装置,连接操作引起的位置偏移和由于基板的收缩导致的位置偏移,连接故障增强,可靠性降低, 总的棒状基板103的形状由矩形形状(lx1xly1)构成,并且连续的电极焊盘通过在Y方向上的Ts进行衬衫,由此面板阵列基板的引线与棒状基板的引线配线可以 提供了高精度连接,并且提供了具有高产量和优异显示特性的电光装置。
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公开(公告)号:US07462517B2
公开(公告)日:2008-12-09
申请号:US11339671
申请日:2006-01-26
申请人: Hisashi Ohtani , Jun Koyama , Shunpei Yamazaki
发明人: Hisashi Ohtani , Jun Koyama , Shunpei Yamazaki
CPC分类号: G02B27/017 , G02F1/13454 , H01L21/02532 , H01L21/02609 , H01L21/02672 , H01L21/2022 , H01L27/1277 , H01L27/1296 , H01L29/04 , H01L29/045 , H01L29/78627 , H01L29/78684
摘要: A high performance circuit is formed by using a TFT with less fluctuation in characteristics, and a semiconductor device including such a circuit is formed. When the TFT is formed, first, a base film and a semiconductor film are continuously formed on a quartz substrate without exposing to the air. After the semiconductor film is crystallized by using a catalytic element, the catalytic element is removed. In the TFT formed in such a process, fluctuation in electrical characteristics such as a threshold voltage and a subthreshold coefficient is extremely small. Thus, it is possible to form a circuit, such as a differential amplifier circuit, which is apt to receive an influence of characteristic fluctuation of a TFT.
摘要翻译: 通过使用特性波动较小的TFT形成高性能电路,形成包括这种电路的半导体器件。 当形成TFT时,首先在石英衬底上连续地形成基膜和半导体膜,而不暴露于空气。 在通过使用催化元素使半导体膜结晶之后,除去催化元素。 在这种处理中形成的TFT中,诸如阈值电压和亚阈值系数的电特性波动极小。 因此,可以形成诸如差分放大器电路的电路,其容易受到TFT的特性波动的影响。
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公开(公告)号:US07456430B1
公开(公告)日:2008-11-25
申请号:US09544801
申请日:2000-04-07
申请人: Shunpei Yamazaki , Jun Koyama , Toru Takayama , Toshiji Hamatani
发明人: Shunpei Yamazaki , Jun Koyama , Toru Takayama , Toshiji Hamatani
IPC分类号: H01L29/04
CPC分类号: G02F1/13454 , G02F1/136286 , G02F1/1368 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78621 , H01L29/78627 , H01L29/78645 , H01L29/78684
摘要: The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit TFT.
摘要翻译: 本发明主要提供允许用于有源矩阵型显示装置的大尺寸屏幕的栅极电极和栅极布线,其中为了实现该目的,本发明的结构是在同一基板上具有像素TFT 设置在显示区域和设置在显示区域周围的驱动电路TFT,其中像素TFT和驱动电路TFT的栅电极由第一导电层形成,栅电极通过与形成的栅极布线的连接器电接触 并且连接器设置在像素TFT和驱动电路TFT的沟道形成区域的外侧。
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公开(公告)号:US07456056B2
公开(公告)日:2008-11-25
申请号:US10288516
申请日:2002-11-06
申请人: Shunpei Yamazaki , Satoshi Teramoto , Jun Koyama , Yasushi Ogata , Masahiko Hayakawa , Mitsuaki Osame , Hisashi Ohtani , Toshiji Hamatani
发明人: Shunpei Yamazaki , Satoshi Teramoto , Jun Koyama , Yasushi Ogata , Masahiko Hayakawa , Mitsuaki Osame , Hisashi Ohtani , Toshiji Hamatani
CPC分类号: H01L21/02686 , H01L21/02532 , H01L21/2022 , H01L21/28158 , H01L21/3221 , H01L21/3226 , H01L27/12 , H01L27/1203 , H01L27/1277 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L29/78675
摘要: A novel and very useful method for forming a crystal silicon film by introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and for eliminating or reducing the metal element existing within the crystal silicon film thus obtained is provided. The method for fabricating a semiconductor device comprises steps of intentionally introducing the metal element which promotes crystallization of silicon to the amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain the crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the region from which the thermal oxide film has been eliminated by implementing another thermal oxidation.
摘要翻译: 提供了一种通过引入促进硅结晶到非晶硅膜并用于消除或还原存在于如此获得的晶体硅膜内的金属元素的金属元素来形成晶体硅膜的新颖且非常有用的方法。 制造半导体器件的方法包括以下步骤:有意地引入促进硅结晶到非晶硅膜的金属元素,并通过第一热处理使非晶硅膜结晶以获得晶体硅膜; 通过在氧化气氛中进行第二次热处理来消除或减少存在于晶体硅膜内的金属元素; 消除在前一步骤中形成的热氧化膜; 并通过进行另一次热氧化,在已经除去热氧化膜的区域的表面上形成另一个热氧化膜。
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公开(公告)号:US20080191959A1
公开(公告)日:2008-08-14
申请号:US12068400
申请日:2008-02-06
申请人: Jun Koyama , Shunpei Yamazaki
发明人: Jun Koyama , Shunpei Yamazaki
CPC分类号: H01Q1/2225 , H01Q1/2283
摘要: An object is to provide a semiconductor device in which even in the case where a plurality of antennas are provided, there is no limitation on the layout of the antennas so that disconnection between an integrated circuit portion and the antenna and reduction in a communication distance from a communication device can be prevented. An integrated circuit portion which includes a thin film transistor is provided on a first surface of an insulating base. A first antenna is provided over the integrated circuit portion. A second antenna is provided over a second surface of the base. The first antenna is connected to the integrated circuit potion. The second antenna is connected to the integrated circuit portion through a through hole formed in the base. The first antenna and the second antenna overlap with the integrated circuit portion.
摘要翻译: 目的在于提供一种半导体器件,其中即使在设置多个天线的情况下,也不限制天线的布局,使得集成电路部分和天线之间的断开与通信距离的减小 可以防止通信装置。 包含薄膜晶体管的集成电路部分设置在绝缘基底的第一表面上。 在集成电路部分上提供第一天线。 第二天线设置在基座的第二表面上。 第一个天线连接到集成电路部分。 第二天线通过形成在基座中的通孔连接到集成电路部分。 第一天线和第二天线与集成电路部分重叠。
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