公开(公告)号：US10608090B2

公开(公告)日：2020-03-31

申请号：US16137399

申请日：2018-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Chen-Chih Fan ,  Nhan Do

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/265 ,  H01L27/11546 ,  H01L27/11521

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

公开(公告)号：US10600484B2

公开(公告)日：2020-03-24

申请号：US15849268

申请日：2017-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

公开(公告)号：US10580491B2

公开(公告)日：2020-03-03

申请号：US16015020

申请日：2018-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

IPC: G11C5/08 ,  G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423

Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

公开(公告)号：US20200051636A1

公开(公告)日：2020-02-13

申请号：US16550253

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20200013883A1

公开(公告)日：2020-01-09

申请号：US16576389

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11536 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20200013789A1

公开(公告)日：2020-01-09

申请号：US16578104

申请日：2019-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US20190355424A1

公开(公告)日：2019-11-21

申请号：US16042000

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/16 ,  G11C16/04

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

公开(公告)号：US20190326305A1

公开(公告)日：2019-10-24

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： FENG ZHOU ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/66

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US10446246B2

公开(公告)日：2019-10-15

申请号：US15990220

申请日：2018-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US20190214397A1

公开(公告)日：2019-07-11

申请号：US16208072

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Andy Liu ,  Xian Liu ,  Chunming Wang ,  Melvin Dao ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L23/53295 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/42336

Abstract: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.