公开(公告)号：US11171157B1

公开(公告)日：2021-11-09

申请号：US16866727

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L27/11595 ,  H01L27/11592 ,  H01L27/1158 ,  H01L27/11597 ,  H01L27/11556 ,  H01L27/11553 ,  H01L27/11524

Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

公开(公告)号：US20210343636A1

公开(公告)日：2021-11-04

申请号：US17378357

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/118 ,  H01L27/02

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US11107859B2

公开(公告)日：2021-08-31

申请号：US16531482

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Mauricio Manfrini

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a magnetic tunnel junction (MTJ) device disposed within a dielectric structure over a substrate. The MTJ device has a MTJ disposed between a first electrode and a second electrode. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector is configured to allow current to flow through the MTJ device along a first direction. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The second unipolar selector is configured to allow current to flow through the MTJ device along a second direction opposite the first direction.

公开(公告)号：US11037920B2

公开(公告)日：2021-06-15

申请号：US16744975

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Jung-Chan Yang ,  Lee-Chung Lu ,  Po-Hsiang Huang ,  Chun-Chen Chen

IPC: H01L27/02 ,  H01L27/118 ,  G06F30/394 ,  G06F30/392

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US10991756B2

公开(公告)日：2021-04-27

申请号：US16411706

申请日：2019-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Min Cao ,  Randy Osborne

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

公开(公告)号：US20210111175A1

公开(公告)日：2021-04-15

申请号：US17129763

申请日：2020-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/768 ,  H01L27/22 ,  H01L23/525 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US10756174B2

公开(公告)日：2020-08-25

申请号：US15613339

申请日：2017-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos ,  Chung-Te Lin

IPC: H01L21/82 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.

公开(公告)号：US10707199B2

公开(公告)日：2020-07-07

申请号：US16391057

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  G06F30/392 ,  H01L27/118 ,  G06F111/20 ,  G06F119/18

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US10700125B2

公开(公告)日：2020-06-30

申请号：US16416529

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

公开(公告)号：US10522642B2

公开(公告)日：2019-12-31

申请号：US15623539

申请日：2017-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Chung-Te Lin ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/302 ,  H01L29/06

Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.