公开(公告)号：US20230019415A1

公开(公告)日：2023-01-19

申请号：US17648236

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Cheng-I Chu ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/66

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

公开(公告)号：US11508831B2

公开(公告)日：2022-11-22

申请号：US17120869

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yi-Hsiu Liu ,  Tsung-Lin Lee ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/51

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

公开(公告)号：US20220367410A1

公开(公告)日：2022-11-17

申请号：US17497050

申请日：2021-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/265 ,  H01L21/78 ,  H01L21/683 ,  H01L25/00

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

公开(公告)号：US20220367215A1

公开(公告)日：2022-11-17

申请号：US17532104

申请日：2021-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  H01L21/683

Abstract: A method of forming a semiconductor device includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. A push pin is extended through the first wafer chuck to distort the first wafer. A surface profile distortion of the first wafer is measured with a first surface profiler. A vacuum pressure of a vacuum zone on the first wafer chuck is adjusted using a measurement of the surface profile distortion. The first wafer chuck is moved towards the second wafer chuck so that the first wafer physically contacts the second wafer, and the first wafer is bonded to the second wafer.

公开(公告)号：US11502000B2

公开(公告)日：2022-11-15

申请号：US17001247

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

公开(公告)号：US20220359755A1

公开(公告)日：2022-11-10

申请号：US17813888

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jiang ,  Meng-Han Chou

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/768 ,  H01L29/49

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US20220359286A1

公开(公告)日：2022-11-10

申请号：US17814981

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

公开(公告)号：US20220352321A1

公开(公告)日：2022-11-03

申请号：US17869321

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Che-Fu Chiu ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/10 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L21/8238

Abstract: A method of forming a semiconductor device includes implanting dopants of a first conductivity type into a semiconductor substrate to form a first well, epitaxially growing a channel layer over the semiconductor substrate, forming a fin from the second semiconductor material, and forming a gate structure over a channel region of the fin. The semiconductor substrate includes a first semiconductor material. Implanting the dopants may be performed at a temperature in a range of 150° C. to 500° C. The channel layer may include a second semiconductor material. The channel layer may be doped with dopants of the first conductivity type.

公开(公告)号：US20220344197A1

公开(公告)日：2022-10-27

申请号：US17532511

申请日：2021-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/687 ,  H01L21/683 ,  H01L21/67

Abstract: A method includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. The second wafer is brought into physical contact with the first wafer. A relative distance between the first wafer and the second wafer is monitored using a distance sensor. A pressure of a vacuum zone on the second wafer chuck is controlled using feedback from the distance sensor. The bonded first wafer and second wafer are removed from the first wafer chuck.

公开(公告)号：US20220230926A1

公开(公告)日：2022-07-21

申请号：US17150018

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Yu Huang ,  Han-De Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.