公开(公告)号：US20220310467A1

公开(公告)日：2022-09-29

申请号：US17333399

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/311

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US20220302066A1

公开(公告)日：2022-09-22

申请号：US17338872

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Cho ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L23/48

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

公开(公告)号：US11410953B2

公开(公告)日：2022-08-09

申请号：US16983282

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ho ,  Yi-Wen Wu ,  Chien Ling Hwang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC: H01L21/56 ,  H01L27/112 ,  H01L23/31 ,  H01L21/48 ,  H01L21/3105 ,  H01L25/065 ,  H01L27/02 ,  H01L23/00

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

公开(公告)号：US11322479B2

公开(公告)日：2022-05-03

申请号：US16907317

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50 ,  H01L21/48

Abstract: A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias.

公开(公告)号：US20220082939A1

公开(公告)日：2022-03-17

申请号：US17021222

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: G03F7/031 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  C08K5/375

Abstract: A method of manufacturing a semiconductor device includes forming a polymer mixture over a substrate, curing the polymer mixture to form a polymer material, and patterning the polymer material. The polymer mixture includes a polymer precursor, a photosensitizer, a cross-linker, and a solvent. The polymer precursor may be a polyamic acid ester. The cross-linker may be tetraethylene glycol dimethacrylate. The photosensitizer includes 4-phenyl-2-(piperazin-1-yl)thiazole. The mixture may further include an additive.

公开(公告)号：US20210384075A1

公开(公告)日：2021-12-09

申请号：US17409010

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

公开(公告)号：US20210375767A1

公开(公告)日：2021-12-02

申请号：US16885291

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ho ,  Hung-Jui Kuo ,  Tzung-Hui Lee

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

公开(公告)号：US11164814B2

公开(公告)日：2021-11-02

申请号：US16352843

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Chu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Wei-Chih Chen

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/522

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

公开(公告)号：US11127688B2

公开(公告)日：2021-09-21

申请号：US16547611

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Hung-Jui Kuo ,  Ming-Tan Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The redistribution structure is electrically connected to the semiconductor die. The redistribution structure includes dielectric layers, conductive traces and seal patterns. The conductive traces are embedded in the dielectric layers. At least one conductive trace of the conductive traces includes a via pattern and a routing pattern. The seal patterns are disposed on the conductive traces. One seal pattern of the seal patterns is disposed between a top surface of the routing pattern and a first dielectric layer of the dielectric layers.

公开(公告)号：US11114407B2

公开(公告)日：2021-09-07

申请号：US16009211

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Yu Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Yung-Chi Chu

IPC: H01L23/00 ,  H01L23/544 ,  H01L25/065

Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.