公开(公告)号：US20240387193A1

公开(公告)日：2024-11-21

申请号：US18789076

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Ming-Tan Lee ,  Chen-Cheng Kuo ,  De-Yuan Lu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.

公开(公告)号：US11699598B2

公开(公告)日：2023-07-11

申请号：US17120458

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US10692838B2

公开(公告)日：2020-06-23

申请号：US16228799

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50 ,  H01L21/48

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip, a first adhesive layer, a second adhesive layer and a molding layer. The first adhesive layer is disposed on a first surface of the first chip and a second adhesive layer is disposed on a second surface of the second chip, wherein the first adhesive layer and the second adhesive layer have different thickness, and a total thickness of the first chip and the first adhesive layer is substantially equal to a total thickness of the second chip and the second adhesive layer. The molding layer encapsulates the first chip, the second chip, the first adhesive layer and the second adhesive layer.

公开(公告)号：US20230307251A1

公开(公告)日：2023-09-28

申请号：US18324686

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2225/06568

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US20220278031A1

公开(公告)日：2022-09-01

申请号：US17663970

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US11322479B2

公开(公告)日：2022-05-03

申请号：US16907317

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50 ,  H01L21/48

Abstract: A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias.

公开(公告)号：US10276428B2

公开(公告)日：2019-04-30

申请号：US15688817

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/538 ,  H01L21/78 ,  H01L23/532 ,  H01L23/00

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US10937688B2

公开(公告)日：2021-03-02

申请号：US16396793

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L23/053 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/538 ,  H01L21/78 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US20190295884A1

公开(公告)日：2019-09-26

申请号：US16396793

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/538 ,  H01L21/78 ,  H01L21/02 ,  H01L23/532 ,  H01L23/31

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US20190148341A1

公开(公告)日：2019-05-16

申请号：US16228799

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip, a first adhesive layer, a second adhesive layer and a molding layer. The first adhesive layer is disposed on a first surface of the first chip and a second adhesive layer is disposed on a second surface of the second chip, wherein the first adhesive layer and the second adhesive layer have different thickness, and a total thickness of the first chip and the first adhesive layer is substantially equal to a total thickness of the second chip and the second adhesive layer. The molding layer encapsulates the first chip, the second chip, the first adhesive layer and the second adhesive layer.