公开(公告)号：US09685337B2

公开(公告)日：2017-06-20

申请号：US15243986

申请日：2016-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

公开(公告)号：US09384985B2

公开(公告)日：2016-07-05

申请号：US14334680

申请日：2014-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin ,  An-Chi Liu ,  Hsiao-Pang Chou

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L21/28088 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

Abstract translation: 用于抛光和氧化的金属浇口工艺包括以下步骤。 在衬底上形成具有沟槽的第一电介质层。 依次形成阻挡层和金属层以覆盖沟槽和第一介电层。 执行包括浓度为0〜0.5重量％（重量％）的H 2 O 2的浆料的第一化学机械抛光工艺，以抛光金属层直到暴露第一​​介电层上的阻挡层。 执行包括浓度高于1重量％（重量％）的H 2 O 2的浆料的第二化学机械抛光方法以抛光阻挡层以及氧化残留在沟槽中的金属层的表面，直到第一介电层 被暴露，从而在金属层上形成金属氧化物层。

公开(公告)号：US20160172496A1

公开(公告)日：2016-06-16

申请号：US14599556

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Chun-Hsien Lin ,  Chen-Yi Weng

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.

Abstract translation: 具有外延结构的场效应晶体管包括鳍状结构和横跨鳍状结构的金属栅极。 金属栅极包括设置在金属栅极底部两侧的一对凹陷区域。

公开(公告)号：US09054187B2

公开(公告)日：2015-06-09

申请号：US14089771

申请日：2013-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

公开(公告)号：US20150061041A1

公开(公告)日：2015-03-05

申请号：US14017001

申请日：2013-09-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Lin ,  Min-Hsien Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/2855 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

Abstract translation: 公开了一种形成半导体器件的方法。 提供其上具有介电层的基板。 电介质层在其中具有栅极沟槽，栅极电介质层形成在栅极沟槽的底部。 工作功能金属层和顶部阻挡层依次形成在栅极沟槽中。 对顶部阻挡层进行处理以形成含硅顶部阻挡层。 在栅极沟槽中形成低电阻率金属层。

公开(公告)号：US08952451B2

公开(公告)日：2015-02-10

申请号：US14135588

申请日：2013-12-20

Applicant: United Microelectronics Corp.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

Abstract translation: 具有金属栅极的半导体器件包括具有形成在其上的第一栅极沟槽和第二栅极沟槽的衬底，分别形成在第一栅极沟槽和第二栅极沟槽中的栅极电介质层，形成在栅极上的第一功函数金属层 第一栅极沟槽和第二栅极沟槽中的介电层，分别形成在第一栅极沟槽和第二栅极沟槽中的第二功函数金属层和形成在第二功函数金属层上的填充金属层。 第二栅极沟槽的开口宽度大于第一栅极沟槽的开口宽度。 第一栅极沟槽中的第二功函数金属层的上部区域比第一栅极沟槽中的第二功函数金属层的下部区域宽。

公开(公告)号：US20140256136A1

公开(公告)日：2014-09-11

申请号：US13786485

申请日：2013-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Chun-Hsien Lin ,  Chien-Ting Lin

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/31053 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.

Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，在基板上形成多层结构; 那么，在多层结构上形成牺牲图案，在牺牲图案的侧壁上形成隔离物并且设置在多层结构上，去除牺牲图案，将间隔物用作盖层以蚀刻 多层结构的部分，然后多层结构用作覆盖层以蚀刻基底并在基底中形成至少一个翅片结构。

公开(公告)号：US20140113425A1

公开(公告)日：2014-04-24

申请号：US13656764

申请日：2012-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L21/336

CPC classification number: H01L21/823412 ,  H01L21/265 ,  H01L21/823425 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes the following steps. At first, at least a gate structure is formed on a substrate. Subsequently, a first material layer and a second material layer sequentially formed on the substrate conformally cover the gate structure. Subsequently, an implantation process is performed on the second material layer, and a wet etching process is further performed to remove a part of the second material layer to form a remaining second material layer. Furthermore, a dry etching process is performed to remove a part of the remaining second material layer to form a partial spacer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，在基板上形成至少一个栅极结构。 随后，依次形成在基板上的第一材料层和第二材料层共形地覆盖栅极结构。 随后，对第二材料层进行注入工艺，并且进一步执行湿蚀刻工艺以去除第二材料层的一部分以形成剩余的第二材料层。 此外，进行干蚀刻处理以去除剩余的第二材料层的一部分以形成部分间隔物。

公开(公告)号：US12289088B2

公开(公告)日：2025-04-29

申请号：US17393407

申请日：2021-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hon-Huei Liu ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H03H3/08 ,  H03H9/02

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

公开(公告)号：US12261169B2

公开(公告)日：2025-03-25

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.