Abstract:
The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.
Abstract:
An array field emitter device utilizes field emission devices disposed in a matrix or array each comprising an opening in an insulating layer with an upwardly extended cathode with a tip disposed centrally within the opening and a gate electrode substantially concentric with each the cathode tip and having a lip extending into the opening forming a downwardly descending lip projection. Such an array display device can be of the multiplex driven type or can be of the active matrix type.
Abstract:
Apparatus including a diamond semiconductor material bipolar transistor having associated therewith a distally disposed iso-collector. The iso-collector, when operated with a suitable voltage, provides a communicating electric field to the bipolar transistor collector which, in concert with a voltage coupled to the transistor base places the apparatus in an ON mode to induce electrons to be emitted from the collector and to be subsequently collected at the iso-collector. An iso-base is optionally, distally disposed relative to the base of the bipolar transistor.
Abstract:
An image display comprises a plurality of picture elements arranged in a matrix and each connected to a switching thin film transistor and a capacitor. The switching thin film transistor is controlled to drive the corresponding picture element. The image display is capable of areal luminance and of displaying images in a satisfactorily high brightness.
Abstract:
An electronic device employing controlled cold-cathode field-induced electron emission device(s) is set forth wherein controlling sources, drivers, select logic, and interconnecting lines and paths are integrated directly within a single structure.
Abstract:
A field emission pixel includes a cathode on which a field emitter emitting electrons is formed, an anode on which a phosphor absorbing electrons from the field emitter is formed, and a thin film transistor (TFT) having a source connected to a current source in response to a scan signal, a gate receiving a data signal, and a drain connected to the field emitter. The field emitter is made of carbon material such as diamond, diamond like carbon, carbon nanotube or carbon nanofiber. The cathode may include multiple field emitters, and the TFT may include multiple transistors having gates to which the same signal is applied, sources to which the same signal is applied, and drains respectively connected to the field emitters. An active layer of the TFT is made of a semiconductor film such as amorphous silicon, micro-crystalline silicon, polycrystalline silicon, wide-band gap material like ZnO, or an organic semiconductor.
Abstract:
An electron emission device and display including the same include a substrate; a cathode electrode including a first electrode portion formed on the substrate and having opening portions, and second electrode portions placed within respective ones of the opening portions such that the second electrodes are separated from the first electrode; a resistance layer electrically interconnecting the first electrode portion and the second electrode portions of the cathode electrode; and electron emission regions electrically connected to the second electrode portions. A width of the second electrode portions or of the resistance layer between the first and second electrode portions varies along a longitudinal direction of the cathode electrode.
Abstract:
A system and method for addressing individual electron emitters in an emitter array is disclosed. The system includes an emitter array comprising a plurality of emitter elements arranged in a non-rectangular layout and configured to generate at least one electron beam and a plurality of extraction grids positioned adjacent to the emitter array, each extraction grid being associated with at least one emitter element to extract the at least one electron beam therefrom. The field emitter array system also includes a plurality of voltage control channels connected to the plurality of emitter elements and the plurality of extraction grids such that each of the emitter elements and each of the extraction grids is individually addressable. In the field emitter array system, the number of voltage control channels is equal to the sum of a pair of integers closest in value whose product equals the number of emitter elements.
Abstract:
A field emitter array structure is provided. The field emitter array structure includes a plurality of vertical un-gated transistor structures formed on a semiconductor substrate. The semiconductor substrate includes a plurality of vertical pillar structures to define said un-gated transistor structures. A plurality of emitter structures are formed on said vertical un-gated transistor structures. Each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical ungated transistor structure to effectively provide high dynamic resistance with large saturation currents.