Lamp filament having a pitch gradient and method of making

    公开(公告)号:US12198922B2

    公开(公告)日:2025-01-14

    申请号:US17947819

    申请日:2022-09-19

    Abstract: Examples disclosed herein relate to a to a pitch gradient in a lamp filament, and a method of making. In one implementation, a lamp has a bulb filled with a gas. A filament is disposed within the bulb. The filament has a plurality of coils that include a first coil having a first point. The plurality of coils includes a second coil having a second point, and a third coil having a third point. The pitch gradient is defined by a first pitch between the second point and the first point, and a second pitch between the third point and the second point. The second pitch is greater than the first pitch. The second point is 360 degrees away from the first point. The third point is 360 degrees from the second point. A terminal coil is electrically coupled to at least the first coil, the second coil, and the third coil.

    Electrochemical deposition systems with enhanced crystallization prevention features

    公开(公告)号:US12195867B2

    公开(公告)日:2025-01-14

    申请号:US17538245

    申请日:2021-11-30

    Abstract: Electrochemical deposition systems and methods are described that have enhanced crystallization prevention features. The systems may include a bath vessel operable to hold an electrochemical deposition fluid having a metal salt dissolved in water. The systems may also include sensors including a thermometer and concentration sensor operable to measure characteristics of the electrochemical deposition fluid. The systems further include a computer configured to perform operations that include receiving system data from the electrochemical system and generating a control signal to change a characteristic of the electrochemical deposition fluid to prevent crystallization of a metal salt in the fluid. The computer generates the control signal based on processing that may include comparing an actual metal salt concentration in the electrochemical deposition fluid to a theoretical solubility limit for the metal salt in the fluid.

    Liquid dispersion of quantum dot particles

    公开(公告)号:US12195635B1

    公开(公告)日:2025-01-14

    申请号:US18417560

    申请日:2024-01-19

    Abstract: Liquid dispersions of quantum dot particles include an acrylic medium having a boiling point in a range of from greater than or equal to 100° C. to less than or equal to 500° C., quantum dot particles dispersed in the acrylic medium, a photo-initiator, and a surface additive. The liquid dispersions of quantum dot particles are useful as stable liquid formulations that resist gelling for spin-coating and ink-jet printing of color conversion layers in the manufacture of LED and micro-LED panels for advanced displays. Methods of manufacturing light-emitting devices using the liquid dispersions of quantum dot particles are also disclosed.

    TAPERED ANTI-REFLECTION COATING THAT PRESERVES IMAGE SHARPNESS IN WAVEGUIDE COMBINERS

    公开(公告)号:US20250012960A1

    公开(公告)日:2025-01-09

    申请号:US18746195

    申请日:2024-06-18

    Abstract: Embodiments of the disclosure provided herein include waveguide combiners. More specifically, embodiments described herein provide for waveguide combiners with a waveguide layer and a coating having a tapered portion disposed thereover. The waveguide includes one or more gratings, the one or more gratings including a plurality of grating structures disposed over a waveguide substrate, wherein the grating structures include a waveguide material, and the plurality of grating structures include exterior grating structures at outer edges of the one or more gratings. A waveguide layer is disposed over the waveguide substrate between the exterior grating structures and an edge of the waveguide substrate, the waveguide layer including the waveguide material, and a coating disposed over the waveguide layer, the coating having a tapered portion that is tapered from at least one of the exterior grating structures to a planar portion of the coating.

    CHARACTERIZING DEFECTS IN SEMICONDUCTOR LAYERS

    公开(公告)号:US20250006563A1

    公开(公告)日:2025-01-02

    申请号:US18882362

    申请日:2024-09-11

    Inventor: Milan Pesic

    Abstract: A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.

    FACE-UP WAFER ELECTROCHEMICAL PLANARIZATION APPARATUS

    公开(公告)号:US20250001547A1

    公开(公告)日:2025-01-02

    申请号:US18883149

    申请日:2024-09-12

    Abstract: Exemplary substrate electrochemical planarization apparatuses may include a chuck body defining a substrate support surface. The apparatuses may include a retaining wall extending from the chuck body. The apparatuses may include an electrolyte delivery port disposed radially inward of the retaining wall. The apparatuses may include a spindle that is positionable over the chuck body. The apparatuses may include an end effector coupled with a lower end of the spindle. The end effector may be conductive. The apparatuses may include an electric contact extending from the chuck body or retaining wall. The apparatuses may include a current source. The current source may be configured to provide an electric current to an electrolyte within an open interior defined by the retaining wall.

    Methods for copper doped hybrid metallization for line and via

    公开(公告)号:US12183631B2

    公开(公告)日:2024-12-31

    申请号:US17839817

    申请日:2022-06-14

    Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

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