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    RANK-1 LATTICE SAMPLING
    141.
    发明公开
    RANK-1 LATTICE SAMPLING 审中-公开

    公开(公告)号：US20240354912A1

    公开(公告)日：2024-10-24

    申请号：US18760184

    申请日：2024-07-01

    Applicant: NVIDIA Corporation

    Inventor： Alexander Georg Keller ,  Carsten Alexander Waechter ,  Nikolaus Binder

    IPC: G06T5/77 ,  G06T11/00

    CPC classification number: G06T5/77 ,  G06T11/001 ,  G06T2207/10024 ,  G06T2207/20084

    Abstract: In photorealistic image synthesis by light transport simulation, the colors of each pixel are an integral of a high-dimensional function. However, the functions to integrate contain discontinuities that cannot be predicted efficiently. In practice, the pixel colors are estimated by using Monte Carlo and quasi-Monte Carlo methods to sample light transport paths that connect light sources and cameras and summing up the contributions to evaluate an integral. Because of the sampling, images appear noisy when the number of samples is insufficient. A rank-1 lattice sequence provides sample locations and these sample locations can be enumerated (assigned or distributed to pixels) according to a space-filling curve superimposed on a pixel grid. Combinations of space-filling curves and rank-1 lattice sequences reduce correlations, are deterministic, and may be executed for each pixel in parallel. The rank-1 lattice sequence enables real-time light transport simulation, producing high visual quality even for low sampling rates.

    Processing authentication requests for unified access management systems and applications
    145.
    发明授权
    Processing authentication requests for unified access management systems and applications 有权

    公开(公告)号：US12120122B2

    公开(公告)日：2024-10-15

    申请号：US17869641

    申请日：2022-07-20

    Applicant: NVIDIA Corporation

    Inventor： Dhruva Lakshmana Rao Batni

    IPC: H04L67/75 ,  H04L9/40 ,  H04W12/08

    CPC classification number: H04L63/102 ,  H04L63/105

    Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of processing of authorization requests by cloud-based access servers that evaluate access rights to access various cloud-based services. The techniques include but are not limited to generating and processing advanced authorization requests that anticipate future authorization requests that may be generated by cloud-based services. The techniques further include processing of frequently accessed policies and policy data dependencies and preemptive generation and processing of authorization requests that are replicated from existing authorization requests.

    Asynchronous data movement pipeline
    146.
    发明授权
    Asynchronous data movement pipeline 有权

    公开(公告)号：US12118382B2

    公开(公告)日：2024-10-15

    申请号：US17671490

    申请日：2022-02-14

    Applicant: NVIDIA Corporation

    Inventor： Harold Carter Edwards

    IPC: G06F9/54 ,  G06F9/48 ,  G06F9/52

    CPC classification number: G06F9/485 ,  G06F9/524 ,  G06F9/544

    Abstract: Apparatuses, systems, and techniques to parallelize operations in one or more programs with data copies from global memory to shared memory in each of the one or more programs. In at least one embodiment, a program performs operations on shared data and then asynchronously copies shared data to shared memory, and continues performing additional operations in parallel while the shared data is copied to shared memory until an indicator provided by an application programming interface to facilitate parallel computing, such as CUDA, informs said program that shared data has been copied to shared memory.

    Distributed processing of pose graphs for generating high definition maps for navigating autonomous vehicles
    147.
    发明授权
    Distributed processing of pose graphs for generating high definition maps for navigating autonomous vehicles 有权

    公开(公告)号：US12117298B2

    公开(公告)日：2024-10-15

    申请号：US18057619

    申请日：2022-11-21

    Applicant: NVIDIA Corporation

    Inventor： Chen Chen

    IPC: G01C21/32 ,  G05D1/00 ,  G05D1/246

    CPC classification number: G01C21/32 ,  G05D1/246 ,  G05D1/0088 ,  G05D1/0274

    Abstract: According to an aspect of an embodiment, operations may comprise obtaining a pose graph that comprises a plurality of nodes. The operations may also comprise dividing the pose graph into a plurality of pose subgraphs, each pose subgraph comprising one or more respective pose subgraph interior nodes and one or more respective pose subgraph boundary nodes. The operations may also comprise generating one or more boundary subgraphs based on the plurality of pose subgraphs, each of the one or more boundary subgraphs comprising one or more respective boundary subgraph boundary nodes and comprising one or more respective boundary subgraph interior nodes. The operations may also comprise obtaining an optimized pose graph by performing a pose graph optimization. The pose graph optimization may comprise performing a pose subgraph optimization of the plurality of pose subgraphs and performing a boundary subgraph optimization of the plurality of boundary subgraphs.

    LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION
    148.
    发明公开
    LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION 审中-公开

    公开(公告)号：US20240340157A1

    公开(公告)日：2024-10-10

    申请号：US18295537

    申请日：2023-04-04

    Applicant: NVIDIA Corporation

    Inventor： Kedar Rajpathak ,  Tezaswi Raja

    IPC: H04L7/033 ,  H04L7/00

    CPC classification number: H04L7/0331 ,  H04L7/0008 ,  H04L7/0337

    Abstract: Circuitry and method of operating a circuit for monitoring a clock signal having phase-to-phase variation is disclosed. The method comprises adding a fixed number of bits to a pulse count of a reference phase instance for a high or low phase to yield a modified added pulse count when detecting a clock slow abnormality, subtracting the fixed number of bits from the pulse count of the reference phase instance to yield a modified subtracted pulse count when detecting a clock fast abnormality, comparing the modified added pulse count to a pulse count for an immediately subsequent phase instance of the high or low phase count of the clock signal when detecting the clock slow abnormality, and comparing the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the high phase or low phase count of the clock signal when detecting the clock fast abnormality.

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