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    Strained semiconductor device and method of making same
    141.
    发明授权
    Strained semiconductor device and method of making same 有权
    应变半导体器件及其制造方法

    公开(公告)号：US07772676B2

    公开(公告)日：2010-08-10

    申请号：US11473883

    申请日：2006-06-23

    Applicant: Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    Inventor： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor material that varies along an interface between the side portion of the compound semiconductor region and the side portion of the semiconductor body

    Abstract translation: 半导体本体由诸如硅的第一半导体材料形成。 诸如硅锗的化合物半导体区域被嵌入在半导体本体中。 化合物半导体区域包括第一半导体材料和第二半导体材料。 化合物半导体区域具有沿着化合物半导体区域的侧部与半导体本体的侧部之间的界面变化的第二半导体材料的浓度

    STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING
    142.
    发明申请
    STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING 有权
    双嵌入式外延半导体加工中的应力优化

    公开(公告)号：US20100197093A1

    公开(公告)日：2010-08-05

    申请号：US12366356

    申请日：2009-02-05

    Applicant: Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

    Inventor： Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    Abstract: A method of manufacturing dual embedded epitaxially grown semiconductor transistors is provided, the method including depositing a first elongated oxide spacer over first and second transistors of different types, depositing a first elongated nitride spacer on the first oxide spacer, depositing a first photoresist block on the nitride spacer above the first transistor, etching the first nitride spacer above the second transistor, implanting a first halo around the second transistor, etching a first recess in an outer portion of the first halo, stripping the first photoresist above the first transistor, forming a first epitaxially grown semiconductor material in the first recess, implanting a first extension in a top portion of the first material, depositing an elongated blocking oxide over the first and second transistors and first extension, depositing a second photoresist block on the blocking oxide above the second transistor and first extension, etching the blocking oxide and first nitride spacer above the first transistor, implanting a second halo around the first transistor, etching a second recess in an outer portion of the second halo, stripping the second photoresist above the second transistor, forming a second epitaxially grown semiconductor material in the second recess, implanting a second extension in a top portion of the second material, etching the blocking oxide above the second transistor, etching nitride caps from the first and second transistors, depositing a second elongated oxide spacer on the first and second transistors, depositing a second elongated nitride spacer on the second oxide spacer, etching the second nitride spacer to leave nitride sidewalls around gates of the first and second transistors, and implanting deep sources and drains in the first and second transistors.

    Abstract translation: 提供了一种制造双嵌入式外延生长半导体晶体管的方法，所述方法包括在不同类型的第一和第二晶体管上沉积第一细长氧化物间隔物，在第一氧化物间隔物上沉积第一细长氮化物间隔物， 在所述第一晶体管上方蚀刻所述第一氮化物间隔物，在所述第二晶体管的上方蚀刻所述第一氮化物间隔区，在所述第二晶体管周围注入第一卤素，蚀刻所述第一卤素的外部部分中的第一凹陷， 在所述第一凹槽中的第一外延生长的半导体材料，在所述第一材料的顶部中注入第一延伸部，在所述第一和第二晶体管上沉积细长的阻塞氧化物，并且在所述第一和第二晶体管上沉积第一光致抗蚀剂阻挡层， 晶体管和第一延伸，首先蚀刻阻挡氧化物 在所述第一晶体管上方注入氮化物间隔物，在所述第一晶体管的周围注入第二卤素，蚀刻所述第二卤素的外部部分中的第二凹槽，在所述第二晶体管上剥离所述第二光致抗蚀剂，在所述第二凹槽中形成第二外延生长的半导体材料， 在第二材料的顶部注入第二延伸部分，蚀刻第二晶体管上方的阻挡氧化物，蚀刻来自第一和第二晶体管的氮化物盖，在第一和第二晶体管上沉积第二细长氧化物间隔物，沉积第二细长氮化物 隔离第二氧化物间隔物，蚀刻第二氮化物间隔物以在第一和第二晶体管的栅极周围留下氮化物侧壁，以及在第一和第二晶体管中注入深源和漏极。

    METAL GATE TRANSISTORS
    143.
    发明申请
    METAL GATE TRANSISTORS 审中-公开
    金属栅极晶体管

    公开(公告)号：US20100102393A1

    公开(公告)日：2010-04-29

    申请号：US12260095

    申请日：2008-10-29

    Applicant: James Yong Meng LEE ,  Jin-Ping HAN ,  Voon-Yew THEAN

    Inventor： James Yong Meng LEE ,  Jin-Ping HAN ,  Voon-Yew THEAN

    IPC: H01L27/092 ,  H01L21/4763

    CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.

    Abstract translation: 公开了一种包括具有第一和第二有源区的衬底的集成电路。 第一类型的第一晶体管和第二类型的第二晶体管分别设置在第一和第二有源区中。 每个晶体管包括在栅极介电层上方具有金属栅电极的栅极堆叠。 提供了接触第一和第二晶体管的第一和第二栅极介电层的第一和第二栅极阈值电压调节（GTVA）层。 第一GTVA层调谐第一晶体管的栅极阈值电压。 第二晶体管的沟道包括用于调谐第二晶体管的栅极阈值电压的掺杂剂。

    METHOD FOR CONSTRUCTING A DECOMPOSITION DATA STRUCTURE OF MULTIPLE LEVELS OF DETAIL DESIGN FEATURE OF 3D CAD MODEL AND STREAMING THEREOF
    144.
    发明申请
    METHOD FOR CONSTRUCTING A DECOMPOSITION DATA STRUCTURE OF MULTIPLE LEVELS OF DETAIL DESIGN FEATURE OF 3D CAD MODEL AND STREAMING THEREOF 审中-公开
    用于构建3D CAD模型和流程的详细设计特征的多级分解数据结构的方法

    公开(公告)号：US20100088429A1

    公开(公告)日：2010-04-08

    申请号：US12203778

    申请日：2008-09-03

    Applicant: Chih-Hsing CHU ,  Ping-Han WU ,  Yu-Hsuan CHAN ,  Mu-Chi SUNG

    Inventor： Chih-Hsing CHU ,  Ping-Han WU ,  Yu-Hsuan CHAN ,  Mu-Chi SUNG

    IPC: G06F15/16

    CPC classification number: G06F17/50 ,  G06F2217/04

    Abstract: A method for streaming multi-LOD design feature of a 3D-CAD model comprises defining a LOD of a 3D-CAD model with each design feature of the 3D-CAD model, wherein the design feature is the smallest 3D-CAD model constructing unit; constructing the LOD of the 3D-CAD model into a decomposition data structure of LOD design feature recording each design feature of the 3D-CAD model in different LODs, wherein the LOD comprises all unit assembly faces of the design features; constructing a switch face display mechanism controlling whether each design feature of the 3D-CAD model is displayed; and encapsulating a designated design feature into a packet based on users' configuration and transmitting the packet. The invention achieves multi-tier real-time incremental streaming transmission and implements streaming transmission into point-to-point information sharing for collaborative participants to receive information from others to obtain higher level information and share information to others for integrated information sharing efficiency.

    Abstract translation: 3D-CAD模型的流式传输多LOD设计特征的方法包括利用3D-CAD模型的每个设计特征定义3D-CAD模型的LOD，其中设计特征是最小的3D-CAD模型构建单元; 将3D-CAD模型的LOD构建成LOD设计的分解数据结构，其特征在于在不同的LOD中记录3D-CAD模型的每个设计特征，其中LOD包括设计特征的所有单元组装面; 构建控制是否显示3D-CAD模型的每个设计特征的开关面显示机构; 并且基于用户的配置将指定的设计特征封装到分组中并发送分组。 本发明实现多层实时增量流传输，实现流传输到点对点信息共享，为协作参与者接收来自其他人的信息，获得更高层次的信息，并向其他人分享信息以实现综合信息共享效率。

    Semiconductor Fabrication Process Including An SiGe Rework Method
    146.
    发明申请
    Semiconductor Fabrication Process Including An SiGe Rework Method 有权
    包括SiGe返工方法的半导体制造工艺

    公开(公告)号：US20100009502A1

    公开(公告)日：2010-01-14

    申请号：US12172756

    申请日：2008-07-14

    Applicant: Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    Inventor： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    IPC: H01L21/336

    CPC classification number: H01L29/1054 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

    Abstract translation: 一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。 将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。 进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

    Signal activated RNA interference
    150.
    发明申请
    Signal activated RNA interference 有权
    信号激活RNA干扰

    公开(公告)号：US20090234109A1

    公开(公告)日：2009-09-17

    申请号：US12316372

    申请日：2008-12-10

    Applicant: Si-Ping Han ,  Robert D. Barish ,  William A. Goddard

    Inventor： Si-Ping Han ,  Robert D. Barish ,  William A. Goddard

    IPC: C07H21/02

    CPC classification number: C12N15/113 ,  C07H21/02 ,  C12N15/111 ,  C12N2310/11 ,  C12N2310/14 ,  C12N2310/141 ,  C12N2310/3517 ,  C12N2310/3519 ,  C12N2310/53 ,  C12N2320/10

    Abstract: The invention provides compositions and methods for signal activated RNA interference (saRNAi), preferably in vivo. The invention provides polynucleotides that switches between an inactive form and an active form upon covalent or non-covalent interaction with one or more specific chemical signals, such as disease-specific mRNA, miRNA, or other cellular RNA products with sequences that characterize diseased states of the cell. The interaction between the subject polynucleotides and the signals is preferably mediated by hybridization, which exposes, facilitates the formation, and/or allows the formation of a substrate that can be processed by proteins of the RNAi pathway (such as Dicer). The input and output of multiple different polynucleotides of the invention can form an in vivo signaling network. In addition, the multiple input signals can be integrated to modulate the activity of the subject polynucleotides.

    Abstract translation: 本发明提供了用于信号激活的RNA干扰（saRNAi）的组合物和方法，优选在体内。 本发明提供了在与一种或多种特定化学信号共价或非共价相互作用之间切换无活性形式和活性​​形式的多核苷酸，例如疾病特异性mRNA，miRNA或具有表征患病状态的序列的其它细胞RNA产物 细胞。 本发明多核苷酸与信号之间的相互作用优选通过杂交介导，其通过暴露，促进形成和/或允许形成可由RNAi途径的蛋白质（例如Dicer）处理的底物。 本发明的多个不同多核苷酸的输入和输出可以形成体内信号传导网络。 此外，多个输入信号可以被整合以调节受试多核苷酸的活性。

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