公开(公告)号：US20050136337A1

公开(公告)日：2005-06-23

申请号：US10833209

申请日：2004-04-26

Applicant: Yung-Hsiang Wu ,  Je-Ping Hu ,  Ming-Huan Yang ,  Chun-Jung Chen ,  Chien-Hung Liu

Inventor： Yung-Hsiang Wu ,  Je-Ping Hu ,  Ming-Huan Yang ,  Chun-Jung Chen ,  Chien-Hung Liu

IPC: G03F1/08 ,  G03F7/00 ,  G03F9/00 ,  H01L21/027

CPC classification number: G03F1/68 ,  B82Y30/00

Abstract: A method for forming wires of nano-meter grade, wherein by printing or dispensing a solution on a substrate, the solute contained in the solution will form two regions with different thicknesses on the substrate when the solvent has dried. After an etching process is comprehensively applied on the substrate, the region with thinner solute will be completely removed, and only the region with the thicker solute remains as the desired wires. With such a process, the line width of the created wires is narrowed to reach the nano-grade.

Abstract translation: 一种用于形成纳米级线的方法，其中通过在基底上印刷或分配溶液，当溶剂干燥时，溶液中所含的溶质将在基底上形成具有不同厚度的两个区域。 在基板上全面应用蚀刻工艺之后，将完全去除具有较薄溶质的区域，只有具有较厚溶质的区域保持为所需的导线。 通过这样的处理，所产生的线的线宽变窄，达到纳米级。

公开(公告)号：US06876044B2

公开(公告)日：2005-04-05

申请号：US10680023

申请日：2003-10-06

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L31/119

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792

Abstract: An ultraviolet-programmable P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell to be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

Abstract translation: 描述了紫外线可编程P型掩模ROM。 首先提高所有存储器单元的阈值电压，以使每个存储器单元处于通道难以接通的第一逻辑状态，以防止漏电流。 在形成位线和字线之后，通过用UV光照射衬底来编程掩模ROM，以将电子注入到开口下面的ONO层中，以使开口下的存储单元处于第二逻辑状态。

公开(公告)号：US06812507B2

公开(公告)日：2004-11-02

申请号：US10636448

申请日：2003-08-06

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L27148

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  Y10S438/954

Abstract: A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

Abstract translation: 描述能够防止天线效应及其制造的非易失性存储器。 非易失性存储器包括在基板上具有高电阻部分和存储单元部分的字线以及位于字线和基板之间的电荷捕获层。 高电阻部分与衬底中的接地掺杂区域电连接，并且存储单元部分与衬底上的金属互连电连接。

公开(公告)号：US06723603B2

公开(公告)日：2004-04-20

申请号：US10183530

申请日：2002-06-28

Applicant: Chien-Hung Liu ,  Erh-Kun Lai ,  Shyi Shuh Pan ,  Shou Wei Huang ,  Ying Tzoo Chen

Inventor： Chien-Hung Liu ,  Erh-Kun Lai ,  Shyi Shuh Pan ,  Shou Wei Huang ,  Ying Tzoo Chen

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/7887

Abstract: The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.

Abstract translation: 本发明提供了利用多晶硅间隔物的制造工艺来构建具有2bit / cell的闪速存储器的方法。 在本发明中，凹入的多晶硅间隔物用于制造控制栅极下面的不连续的浮动栅极以构建具有2bit / cell的闪速存储器。 本发明的特征在于，多晶硅间隔物的制造工艺被利用以完全以自动对准方式完成浮栅的制造工艺，而无需任何额外的掩模工艺。 此外，该闪速存储器中的每个存储单元可以存储两个位，从而增加存储器容量。

公开(公告)号：US06713315B2

公开(公告)日：2004-03-30

申请号：US10134270

申请日：2002-04-25

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L2100

CPC classification number: H01L27/11266 ,  H01L27/105 ,  H01L27/11293

Abstract: A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.

Abstract translation: 描述了一种用于制造掩模ROM的方法，其中在基板上形成ONO复合层和多个栅极结构。 在栅极结构之间的衬底中形成多个位线，并且在衬底上形成多个字线以与栅极结构电连接。 在其上形成了具有编码窗口的化学气相沉积抗反射涂层（CVD-ARC）和层间电介质层。 然后通过使用UV光在未被CVD-ARC覆盖的电荷捕获层中形成多个带电编码区域来进行编码处理。 然后在编码窗口中形成多个插头。

公开(公告)号：US06666545B2

公开(公告)日：2003-12-23

申请号：US10038909

申请日：2002-01-08

Applicant: Chien-Hung Liu ,  Jian-Chiun Liou ,  Charles C. Chang ,  Je-Ping Hu ,  Chun-Jung Chen

Inventor： Chien-Hung Liu ,  Jian-Chiun Liou ,  Charles C. Chang ,  Je-Ping Hu ,  Chun-Jung Chen

IPC: B41J205

CPC classification number: B41J2/1642 ,  B41J2/14072 ,  B41J2/1601 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2202/13

Abstract: A driver transistor structure of an inkjet print head chip and the method for making the same. Having several body contacts distributed all over the source of an active region of a large area MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an equivalent RB from the MOSFET channel to the body contact is greatly diminished as the distance between them is reduced, thereby preventing the occurrence of a secondary breakdown. Since the body contact is installed inside the active region without defining in advance a body contact region and making the body contact in the field oxide layer outside the active region, about 20% of the driver transistor structure can be saved to lower the average manufacturing cost of each chip.

公开(公告)号：US06642113B1

公开(公告)日：2003-11-04

申请号：US10128742

申请日：2002-04-23

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L2100

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  Y10S438/954

Abstract: A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

Abstract translation: 描述能够防止天线效应及其制造的非易失性存储器。 非易失性存储器包括在基板上具有高电阻部分和存储单元部分的字线以及位于字线和基板之间的电荷捕获层。 高电阻部分与衬底中的接地掺杂区域电连接，并且存储单元部分与衬底上的金属互连电连接。

公开(公告)号：US06627500B1

公开(公告)日：2003-09-30

申请号：US10064796

申请日：2002-08-19

Applicant: Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L218247

CPC classification number: H01L27/11568 ,  H01L27/115 ,  Y10S438/978

Abstract: A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.

Abstract translation: 一种制造氮化物只读存储器的方法。 在衬底上形成包括绝缘层，电荷陷阱层和绝缘层的俘获电介质夹层结构。 在绝缘层中形成具有凹入侧壁的开口。 形成热氧化物层以填充开口，使得凹入的侧壁被完全密封。 因此，电荷陷阱层被绝缘层和热氧化物层密封，以避免控制栅极和电荷陷阱层之间的直接接触，从而防止数据丢失。

公开(公告)号：US06580630B1

公开(公告)日：2003-06-17

申请号：US10165715

申请日：2002-06-07

Applicant: Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan

Inventor： Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan

IPC: G11C1300

CPC classification number: H01L29/66833 ,  G11C16/18 ,  H01L21/28282 ,  H01L29/792

Abstract: The presents invention provides an initialization method of a P-type silicon nitride read only memory. A P-type silicon nitride read only memory is provided. An ultra-violet light is uniformly radiated onto the P-type silicon nitride read only memory. Electron traps are thus evenly distributed in a silicon nitride layer of the P-type silicon nitride read only memory. The P-type silicon nitride read only memory is thus uniformly programmed to a low threshold voltage (Low|Vt|) to achieve the device initialization effect.

Abstract translation: 本发明提供了一种P型氮化硅只读存储器的初始化方法。 提供了P型氮化硅只读存储器。 紫外光均匀地辐射到P型氮化硅只读存储器上。 因此，电子俘获器均匀分布在P型氮化硅只读存储器的氮化硅层中。 因此，P型氮化硅只读存储器被均匀地编程到低阈值电压（Low | Vt |）以实现器件初始化效果。

公开(公告)号：US06413815B1

公开(公告)日：2002-07-02

申请号：US09682069

申请日：2001-07-17

Applicant: Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

Inventor： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

IPC: H01L218242

CPC classification number: H01L21/76808 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of simultaneously forming a dual damascence runner and a metal-insulator-metal (MIM) capacitor on a semiconductor wafer. The semiconductor wafer has a first dielectric layer, which has at least a first conductive layer and at least a bottom electrode of the MIM capacitor. The surfaces of the first conductive layer and the bottom electrode of the MIM capacitor are covered with a barrier layer. A second dielectric layer, a stop layer and a third dielectric layer are formed on the surface of the barrier layer and form a sandwiched structure. A first photoresist layer is formed and the third dielectric layer is anisotropically etched down to the stop layer, thus forming a trench and an opening in the third dielectric layer above the conductive layer and the bottom electrode of the MIM capacitor. A second photoresist layer is formed and the stop layer and the second dielectric layer are etched at a bottom of the opening down to the surface of the barrier layer so as to form an opening of the top electrode. A third photoresist layer is formed and the stop layer, the second dielectric layer and the barrier layer are etched through the contact opening down to the surface of the first conductive layer so as to form a contact hole.

Abstract translation: 一种在半导体晶片上同时形成双重阻力流道和金属 - 绝缘体 - 金属（MIM）电容器的方法。 半导体晶片具有至少具有MIM电容器的第一导电层和至少底部电极的第一电介质层。 MIM电容器的第一导电层和底部电极的表面被阻挡层覆盖。 在阻挡层的表面上形成第二电介质层，阻挡层和第三电介质层，并形成夹层结构。 形成第一光致抗蚀剂层，并且将第三介电层各向异性地向下蚀刻到停止层，从而在MIM电容器的导电层和底部电极上方的第三介电层中形成沟槽和开口。 形成第二光致抗蚀剂层，并且将阻止层和第二介电层在开口的底部蚀刻到阻挡层的表面，以形成顶部电极的开口。 形成第三光致抗蚀剂层，并且通过接触开口将停止层，第二介电层和阻挡层蚀刻到第一导电层的表面，以形成接触孔。