公开(公告)号：US20180082955A1

公开(公告)日：2018-03-22

申请号：US15724367

申请日：2017-10-04

Applicant: International Business Machines Corporation

Inventor： Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  Roger A. Quon ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76849 ,  H01L21/76883

Abstract: Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a CuxTiyNz alloy in the surface. The methods generally include forming a titanium nitride layer on an exposed copper surface followed by annealing to form the CuxTiyNz, alloy in the exposed copper surface. Subsequently, the titanium layer is removed by a selective wet etching.

公开(公告)号：US20180082952A1

公开(公告)日：2018-03-22

申请号：US15813477

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53261

Abstract: A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer is deposited over the adhesion promoting layer. Using a physical vapor deposition process, a cobalt layer is deposited over the ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures.

公开(公告)号：US20180082951A1

公开(公告)日：2018-03-22

申请号：US15645688

申请日：2017-07-10

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/764 ,  H01L21/311

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.

公开(公告)号：US20180076143A1

公开(公告)日：2018-03-15

申请号：US15807793

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal interconnect structure, as well as methods for fabricating the semiconductor device. For example, a method comprises forming a metal interconnect structure in a dielectric layer, and applying a surface treatment to a surface of the metal interconnect structure to form a point defect layer in the surface of the metal interconnect structure. A metallic capping layer is then formed on the point defect layer of the metal interconnect structure, and a thermal anneal process is performed to convert the point defect layer into a metal alloy capping layer by infusion of metal atoms of the metallic capping layer into the point defect layer. The resulting metal alloy capping layer comprises an alloy of metallic materials of the metal capping layer and the metal interconnect structure.

公开(公告)号：US20180061703A1

公开(公告)日：2018-03-01

申请号：US15806314

申请日：2017-11-07

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266

Abstract: An integrated circuit device has a substrate including a dielectric layer patterned with a pattern which includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed on the set of features in the patterned dielectric. A ruthenium layer is disposed on the adhesion promoting layer. A cobalt layer is disposed on the ruthenium layer filling a first portion of the set of features. The cobalt layer has a u-shaped cross section having a thicker bottom layer than side layers. The cobalt layer is formed using a physical vapor deposition process. A metal layer is disposed on the cobalt layer filling a second, remainder portion of the set of features.

公开(公告)号：US20180061702A1

公开(公告)日：2018-03-01

申请号：US15251403

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76825 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.

公开(公告)号：US20180053727A1

公开(公告)日：2018-02-22

申请号：US15424753

申请日：2017-02-03

Applicant: International Business Machines Corporation

Inventor： Daniel C Edelstein ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53209 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266

Abstract: An integrated circuit device includes a substrate including a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A ruthenium cobalt alloy layer is disposed over the adhesion promoting layer. A metal layer is disposed over the ruthenium cobalt alloy layer filling the set of features.

公开(公告)号：US09899327B2

公开(公告)日：2018-02-20

申请号：US15192499

申请日：2016-06-24

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76883

Abstract: A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor at least partially in the dielectric layer includes performing a planarization process. The method further includes treating respective surface areas of the dielectric layer and the metallic conductor, after the planarization process, to modify the respective surface areas of the dielectric layer and the metallic conductor. In one example, the surface treatment is a neutral atom beam treatment.

公开(公告)号：US20180047669A1

公开(公告)日：2018-02-15

申请号：US15792356

申请日：2017-10-24

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L29/20

CPC classification number: H01L23/5252 ,  H01L29/20

Abstract: An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure.

公开(公告)号：US20180040686A1

公开(公告)日：2018-02-08

申请号：US15229209

申请日：2016-08-05

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: Semiconductor devices having MIM capacitor structures are provided, as well as methods for fabricating semiconductor devices having MIM capacitor structures. For example, a semiconductor device includes a first capacitor electrode formed on a substrate, a capacitor insulating layer formed on the first capacitor electrode, and a second capacitor electrode. The second capacitor electrode comprises a layer of metallic material that is formed by application of a surface treatment to a surface of the capacitor insulating layer to convert the surface of the capacitor insulating layer to the layer of metallic material. As an example, the capacitor insulating layer comprises Ta3N5 insulating material, and the second capacitor electrode comprises TaN metallic material.