公开(公告)号：US10452586B2

公开(公告)日：2019-10-22

申请号：US15488929

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F13/40 ,  G06F12/0846 ,  G06F9/54 ,  G06F13/42 ,  G06T1/60 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190317771A1

公开(公告)日：2019-10-17

申请号：US16388444

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/54 ,  G06F12/0866 ,  G06F9/50 ,  G06T1/20 ,  G06F15/16 ,  G06F15/76 ,  G06F9/52 ,  G06F9/46 ,  G06T1/60 ,  G06F12/0897

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

公开(公告)号：US10417734B2

公开(公告)日：2019-09-17

申请号：US15698217

申请日：2017-09-07

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US10403003B2

公开(公告)日：2019-09-03

申请号：US15494812

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Farshad Akhbari

IPC: G06T9/00

Abstract: An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.

公开(公告)号：US10402933B2

公开(公告)日：2019-09-03

申请号：US15494612

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  David M. Cimini ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Abhishek R. Appu

IPC: G06T15/04 ,  G06T1/20 ,  G06T15/00 ,  G06T15/50 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide a way to monitor, by a process monitor, one or more processing factors of one or more client devices hosting one or more user sessions. More particularly, the systems, apparatuses and methods may provide a way to generate, responsively, a scene generation plan based on one or more of a digital representation of an N dimensional space or at least one of the one or more processing factors, and generate, by a global scene generator, a global scene common to the one or more client devices based on the digital representation of the space. The systems, apparatuses and methods may further provide for performing, by a local scene generator, at least a portion of the global illumination based on one or more of the scene generation plan, or application parameters.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10325341B2

公开(公告)日：2019-06-18

申请号：US15493233

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Altug Koker ,  Joydeep Ray

IPC: G06T1/20 ,  G06T15/00

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing units and a pipeline manager to distribute a thread group to the multiple processing units, wherein the pipeline manager is to distribute the thread group as multiple thread sub-groups.

公开(公告)号：US10304154B2

公开(公告)日：2019-05-28

申请号：US15495054

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US10261903B2

公开(公告)日：2019-04-16

申请号：US15489149

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190050308A1

公开(公告)日：2019-02-14

申请号：US15857885

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Michael Derr ,  Gustavo Espinosa ,  Balaji Vembu ,  Richard Shannon ,  Bradley Coffman ,  Daniel Knollmueller

IPC: G06F11/263 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F11/2205 ,  G06F11/2215 ,  G06F11/2284

Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.